CIRCC datasheet(41/70 Pages) SMSC

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Bit 2

Setting this bit to a logic "1" clears all bytes in the

XMIT FIFO and resets its counter logic to 0. The

shift register is not cleared.

This bit is self-

clearing.

Bit 3

Writing to this bit has no effect on the operation of

the UART. The RXRDY and TXRDY pins are not

available on this chip.

Bit 4,5

Reserved

BIT 7

BIT 6

RCVR FIFO

TRIGGER LEVEL

Bit 6,7

These bits are used to set the trigger level for the

RCVR FIFO interrupt.

INTERRUPT IDENTIFICATION REGISTER

(IIR)

Address Offset = 2H, DLAB = X, READ

By accessing this register, the host CPU can

determine the highest priority interrupt and its

source. Four levels of priority interrupt exist. They

are in descending order of priority:

Receiver Line Status (highest priority)

Received Data Ready

Transmitter Holding Register Empty

MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is

pending and the source of that interrupt is stored

in the Interrupt Identification Register (refer to

Table 27 - Interrupt Control Table).

When the

CPU accesses the IIR, the Serial Port freezes all

interrupts

and

indicates

the

highest

priority

pending interrupt to the CPU.

During this CPU

access, even if the Serial Port records new

interrupts, the current indication does not change

until access is completed. The contents of the IIR

are described below.

Bit 0

This bit can be used in either a hardwired

prioritized

polled

environment

indicate

whether an interrupt is pending. When bit 0 is a

logic "0", an interrupt is pending and the contents

of the IIR may be used as a pointer to the

appropriate internal service routine. When bit 0 is

logic "1", no interrupt is pending.

Bits 1 and 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated by

the Interrupt Control Table.

Bit 3

In non-FIFO mode, this bit is a logic "0". In FIFO

mode this bit is set along with bit 2 when a timeout

interrupt is pending.

Bits 4 and 5

These bits of the IIR are always logic "0".

Bits 6 and 7

These two bits are set when the FIFO CONTROL

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