CIRCC datasheet(26/70 Pages) SMSC

26 / 70 page

Active Frame Interrupt, bit 7

When this bit is one, an Active Frame has

occurred (see the Active Frame Indicator section

on page 54).

The Active Frame typically

indicates that the SCE receiver has detected a

valid infrared carrier.

Reading the Interrupt

Identification register resets the Active Frame

Interrupt bit.

EOM Interrupt, bit 6

When this bit is one, an End of Message has

occurred. The EOM bit indicates the end of an

Abort,

FIFO

underruns/overruns

and

DMA

Terminal

Counts.

Reading

the

Interrupt

Identification register resets the EOM bit.

Raw Mode Interrupt, bit 5

When this bit is one, a Raw Mode interrupt has

occurred. The Raw Mode Interrupt indicates that

the Raw Rx Control bit has gone active. Reading

the Interrupt Identification register resets the Raw

Mode Interrupt bit.

FIFO Interrupt, bit 4

When this bit is one, a FIFO Interrupt has

occurred. The FIFO Interrupt indicates that the

FIFO Interrupt Enable is active and either a

TxServReq or a RxServReq has occurred. The

FIFO Interrupt bit is cleared when the interrupt is

disabled; i.e., reading the Interrupt Identification

the FIFO Interrupt section on page 57).

IR Busy, bit 3

The IR Media Busy hardware sets the IR Busy bit

in the IID high if an infrared pulse that is greater

than TPW_MIN has occurred at the receiver input,

except during message transmit or during the IR

Half Duplex Timeout following message transmit.

TPW_MIN can be defined as 20ns#TPW_MIN#30ns

The

Media

Busy

hardware

operates

independently of the IR Rx Pulse Rejection

filters, the programmed receive data rate, or the

state of the ACE or SCE Rx Enables (see Figure

36).

Reading the IID register will reset the IR

Busy bit. The IR Busy bit is also reset following

Master Reset and POR. If the IR Busy Enable

bit is high, the IR Busy Interrupt is enabled onto

the Interrupt Request bus IRQ if the master

Interrupt Enable is also active.

The IR Busy

Enable bit does not affect the IR Busy bit in the

IID.

PROGRAMMER’S NOTE: The IR Busy bit may

be unintentionally activated during IR Mode

changes.

Interrupt Enable Register (Address 2)

Setting any of the bits in this register to one

enables

the

associated

interrupt

(see

the

Interrupt Identification Register).

Interrupts will

only occur if both the interrupt enable bit and the

Master Interrupt Enable bit (see the Master Block

Control Register) are active.

The interrupt enables do not affect the state of

the interrupts, except for the FIFO Interrupt. For

example, a Raw Mode interrupt that occurs while

the Raw Mode Interrupt Enable is inactive will be

visible in the IID register but will not affect IRQ.

Line Status Register(s) (Address 3)

Error Indicators (read-only)

There are eight Line Status Registers at address

Each register is read-only and is accessed

using the three Status Register Address bits,

also

located

this

address.

The

FIFO

Underrun, FIFO Overrun, Frame Error, and

Frame Abort Error flags indicate the status of any

one of eight message frames.

The Error

Indicators, in all registers, are reset following a

Master Reset, Power-On-Reset, and Error Reset

(see the Master Block Control Register).

The

error indicators for the current status register only

(see the Message Count bits) are reset following

a valid start of frame sequence.

CIRCC Datasheet(PDF) 26 Page - SMSC Corporation

CIRCC Datasheet(HTML) 26 Page - SMSC Corporation

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