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CIRCC Datasheet(PDF) 1 Page - SMSC Corporation

Part # CIRCC
Description  Consumer Infrared Communications Controller
PDF  70 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

CIRCC Datasheet(HTML) 1 Page - SMSC Corporation

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CIrCC
Consumer Infrared Communications Controller
FEATURES
Multi-Protocol Serial Communications
Controller
Full IrDA v1.0 Implementation: 2.4 kbps to
115.2 kbps
Consumer Infrared Remote Control Interface
SHARP Amplitude Shift Keyed Infrared
(ASK IR) Interface
Direct Rx/Tx Infrared Diode Control (Raw)
and General Purpose Data Pins
Programmable High-Speed Synchronous
Communications Engine (SCE) with a 32-
Byte FIFO and Programmable Threshold
Programmable DMA Refresh Counter
High-Speed NS16C550A-Compatible
Universal Asynchronous Receiver/
Transmitter Interface (ACE UART) with 16-
Byte Send and Receive FIFOs
ISA Single-Byte and Burst-Mode DMA and
Interrupt-Driven Programmed I/O with Zero
Wait State and String Move Timing
Automatic Transceiver Control
Transmit Pulse Width Limiter
SCE Transmit Delay Timer
IR Media Busy Indicator
GENERAL DESCRIPTION
This document describes the Consumer Infrared
Communications
Controller
(CIrCC)
function,
which is common to a number of SMSC
products. The CIrCC consists of two main
architectural blocks: the ACE 16C550A UART
and a Synchronous Communications Engine
(SCE) (Figure 2). Each Block is supported by its
own unique register set.
The CIrCC UART-driven IrDA SIR and SHARP
ASK modes are backward-compatible with early
SMSC
Super
I/O
and
Ultra
I/O
infrared
implementations. The CIrCC SCE supports IrDA
version 1.0 and consumer IR modes. All of the
SCE modes use DMA. The CIrCC offers flexible
signal routing and programmable output control
through
the
Raw
mode
interface,
General
Purpose Data pins and Output Multiplexer.
Hardware decoding of the NEC PPM Consumer
IR Remote Control format is implemented in the
CIrCC. The CIrCC provides a PME output signal
that is used to indicate the occurrence of a valid
CIR
Wake-up
event.
Chip-level
address
decoding is required to access the CIrCC register
sets.


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