PCD6001 datasheet(36/96 Pages) PHILIPS

36 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6001

10.10.1 IDLE MODE

In the Idle state Timer 0 and Timer 1 and the I2C-bus

controller are still clocked. The CPU status along with all

SFRs, main RAM and AUX RAM registers are preserved.

Leaving the Idle state can be done by any enabled

interrupt or reset. The microcontroller hardware will clear

the Idle flag and start executing the interrupt. When the

interrupt is serviced (RETI instruction) the microcontroller

will execute the next instruction following the instruction

that put the microcontroller in the idle state.

10.10.2 POWER-DOWN MODE

In the Power-down state the clock of the entire

microcontroller with its peripherals is off. The CPU status

along with all SFRs, main RAM and AUX RAM registers

are preserved. Leaving the Power-down state can be done

by any active enabled interrupt source or reset.

The microcontroller hardware will clear the PD flag and

start executing the interrupt. When the interrupt is serviced

(RETI instruction) the microcontroller will execute the

instruction following the instruction that put the

microcontroller in the PD state.

Toggling of the ALE signal (for enhanced EMC

performance) is not supported.

10.10.3 THE WATCHDOG CIRCUITRY

The purpose of the watchdog is to reset the microcontroller

if it enters erroneous states caused by EMI or bugs in the

software that cannot be detected or eliminated.

When enabled the watchdog circuitry will generate a reset

if the user program fails to reload the Watchdog Timer

within a specified length of time known as the watchdog

interval.

The watchdog interval is calculated as follows:

The programmer should implement the following protocol:

1. Write the key value 55H to the WDTKEY SFR to

disable the watchdog.

2. Set the WLE/EW bit to logic 1 to initially enable the

watchdog. WLE/EW now functions as a WLE bit. Only

a reset can clear the EW bit.

3. Enable the Watchdog Timer by writing a value not

equal to 55H to the WDTKEY SFR. This is only

necessary if the previous value of the WDTKEY

4. Enable the load of the WDT SFR by setting the WLE

bit to logic 1.

5. Load the watchdog interval by writing the required

value into the WDT SFR. After the load the WLE bit is

set to logic 0 again by the watchdog hardware. The

value of WDT is 00H after reset.

6. Write a value not equal to 55H to the WDTKEY SFR to

enable the watchdog.

7. Repeat steps 4 and 5 in the user software before the

Watchdog Timer expires.

Note in Metalink emulation mode the watchdog cannot be

used, the watchdog reset will reset the entire chip.

256

WDT

–

()

12 287

microcontroller_CLK

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PCD6001 Datasheet(PDF) 36 Page - NXP Semiconductors

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