PCD6001 datasheet(38/96 Pages) PHILIPS

38 / 96 page

2001 Apr 17

Philips Semiconductors

Product speciﬁcation

Digital telephone answering machine chip

PCD6001

10.11.1 SERIAL CONTROL REGISTER (S1CON)

Two bits are affected by the I2C-bus hardware, the SI bit is set to logic 1 when a serial interrupt is requested, and the

STO bit is set to logic 0 (cleared) when a STOP condition is present on the I2C-bus. The STO bit is also cleared when

ENS1 = 0. When the I2C-bus block is in the Master mode the serial clock frequency is determined by the clock rate bits

CR[2:0].

Table 33 Serial Control Register (SFR address D8H)

Table 34 Description of S1CON bits

76543210

CR2

ENS1

STA

STO

CR1

CR0

BIT

SYMBOL

DESCRIPTION

CR2

Clock rate. This bit along with bits CR1 and CR0 determines the serial clock frequency

when I2C-bus is in Master mode, see Table 35.

ENS1

When this bit is set to logic 0 the I2C-bus is disabled, outputs SDA and SCL are in the

high-impedance state, and P1.6 and P1.7 function as open-drain ports. With this bit set

to logic 1 the I2C-bus is enabled. The P1.6 and P1.7 port latch must be set to logic 1.

5STA

Start ﬂag. When the STA bit is set to logic 1 in Slave mode, the I2C-bus hardware

checks the status of the I2C-bus and generates a START condition if the bus is free. If

STA is set to logic 1 while the I2C-bus is in Master mode, the I2C-bus transmits a

repeated START condition.

4STO

Stop ﬂag. With this bit set to logic 1 while in Master mode a STOP condition is

generated. When a STOP condition is detected on the bus, the I2C-bus hardware clears

the STO ﬂag. In the Slave mode, the STO ﬂag may also be set to logic 1 to recover from

an error condition. In this case no STOP condition is transmitted to the I2C-bus.

However, the I2C-bus hardware behaves as if a STOP condition has been received and

releases SDA and SCL. The I2C-bus then switches to the ‘not addressed’ receiver

mode. The STO ﬂag is automatically cleared by hardware.

3SI

I2C-bus interrupt ﬂag. When this ﬂag is set to logic 1, an acknowledge is returned (i.e.

an interrupt is generated) after any one of the following conditions:

• A start condition is generated in Master mode

• Own slave address received during AA = 1

• General call address received while S1ADR[0] = 1and AA = 1

• Data byte received or transmitted in Master mode (even if arbitration is lost)

• Data byte received or transmitted as selected slave

• Stop or start condition received as selected slave receiver or transmitter.

2AA

Assert Acknowledge. When set to logic 1 an acknowledge will be returned during the

acknowledge clock pulse on SCL when:

• Own slave address is received

• General call address is received while S1ADR[0] = 1

• Data byte is received while device is a selected slave.

With AA = 0 no acknowledge will be returned. Consequently, no interrupt is requested

when the ‘own slave address’ or general call address is received.

CR1

Clock rate. These 2 bits along with the CR2 bit determine the serial clock frequency

when I2C-bus is in Master mode, see Table 35.

CR0

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