PCF5001 datasheet(26/44 Pages) PHILIPS

26 / 44 page

1997 Mar 04

Philips Semiconductors

Product speciﬁcation

POCSAG Paging Decoder

PCF5001

7.19

EEPROM Write operation

The program mode is entered in OFF status by setting the

PD input LOW and the PS input HIGH at any time.

The ‘program’ mode is left and normal operation resumed

by either removing the power supply or setting the PD

input HIGH after the 38th data bit while continuing to clock

the PS input. The three EEPROM arrays can be

programmed in any order. Selection of array is made

during the second and third pulse on the PS input.

The ‘program’ mode has to be left after programming of

each array.

After entering the ‘program’ mode, keeping input PD LOW

during the first pulse on PS selects Memory Write

operation. After selection of the current array an erase

cycle of duration tPEW has to be carried out, during which

the supply voltage at VSS input must be at least VPG.

Program data for the selected array is entered bit by bit

using PD as data input and the rising edge on PS as data

strobe pulse. See Fig.19 for timing during an EEPROM

write operation.

After the last bit a special write cycle of duration tPEW has

to be carried out again, during which the supply voltage at

VSS input must be VPG. During conditions when the supply

voltage is increased to VPG the maximum DC ratings at Vref

must not be exceeded. When the on-chip voltage

converter is enabled a voltage regulator diode or a

damping resistor of sufficiently low impedance has to be

connected between Vref and VSS to limit the voltage level

at Vref during program operation.

7.20

EEPROM Read operation

After entrance to the ‘program’ mode, keeping input PD

HIGH during the first pulse on PS selects Memory Read

operation. After selection of the current array the

programmed data is output bit-by-bit using PD as data

output. A positive edge on PS input switches to the next

bit. See Fig.19 for timing during an EEPROM read

operation.

7.21

Read-back operation via Microcontroller

Interface

In ‘display pager’ mode, the PCF5001 is capable of

delivering the EEPROM contents to an external

microcontroller using the serial interface outputs DO and

DS. The EEPROM data transfer mode is selected by

applying a LOW to input ON and a HIGH to input SK while

pulsing the SR input, and the interface is enabled (IE is

HIGH). The data transfer is started by a logic HIGH level

on SR. The HIGH level on SR must be removed before the

end of the tenth output byte, otherwise the transfer is

aborted and restarted. The minimum pulse duration

corresponds with tSPD in the status interrogation timing

(see Fig.7). The transfer is organized as 15-byte transfers.

The contents of each array are extended to 40 bits by

trailing zeros. The EEPROM data transfer starts with array

1, bit 0. A valid data bit at DO is indicated by a LOW-level

on DS as shown in Fig.20.

During EEPROM Read-back operation, the PCF5001

configuration and the outputs FL, OL are undefined.

After completion of the Read-Back operation, the

PCF5001 will re-enter the programmed configuration.

7.22

Voltage converter

The PCF5001 contains a switched capacitor-type on-chip

voltage converter, which can provide doubled supply

voltage to the external microcontroller and display control

devices. The microcontroller interface signals are level

shifted accordingly.

A capacitor of 100 nF (CS) must be connected between

pins CP and CN while a load capacitor of 10

µF is

connected to Vref as shown in Fig.23. The voltage

converter operates in ‘display pager’ mode only, when

enabled by programming SPF08 (see Table 9).

PCF5001 Datasheet(PDF) 26 Page - NXP Semiconductors

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