VT6103 datasheet(24/46 Pages) VIA

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VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver

Revision 1.1 April 15, 2002

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Functional Description

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802.3u MII

The VT6103 incorporates the Media Independent Inter-face

(MII) as specified in clause 22 of the IEEE 802.3u standard.

This interface may be used to connect PHY devices to MAC

or repeater devices in 10/100 Mb/s systems.

This section

describes both the serial MII management interface as well as

the nibble wide MII data interface. The management interface

of the MII allows the configuration and control of multiple

PHY devices, the gathering of status and error information,

and the determination of the type and abilities of the attached

PHY(s).

The nibble wide MII data interface consists of a

receive bus and a transmit bus each with control signals to

facilitate data transfer between the PHY and the upper layer

(MAC or repeater.) The VT6103 supports the MII interrupt

function.

Serial Management Register Access

The serial MII specification defines a set of thirty-two 16-bit

status and control registers that are accessible through the

serial management data interface pins MDC and MDIO. The

VT6103 implements all the required MII registers as well as

several optional registers. These registers are fully described

in the registers section of this document. A description of the

serial management access protocol follows.

Serial Management Access Protocol

The serial control interface consists of two pins, Management

Data Clock (MDC) and Management Data Input/Output

(MDIO). MDC has a maximum clock rate of 10 MHz and no

minimum rate. The MDIO line is bidirectional and may be

shared by up to 32 devices.

The MDIO frame format is

shown in IEEE802.3, section 22.2.4.4. The MDIO pin has an

internal pull-up resistor (1.5Kohm) which will pull MDIO

high during IDLE and turnaround. In order to initialize the

MDIO interface, the station management entity sends a

sequence of 32 contiguous logic ones on MDIO to provide the

VT6103 with a sequence that can be used to establish

synchronization. This preamble may be generated either by

driving MDIO high for 32 consecutive MDC clock cycles, or

by simply allowing the MDIO pull-up resistor to pull the

MDIO pin high during which time 32 MDC clock cycles are

provided. In addition, 32 MDC clock cycles should be used if

an invalid start, pop code, or turn-around bit is detected.

The VT6103 waits until it has received this preamble

sequence before responding to any other transaction. Once

the VT6103 serial management port has initialized, no further

preamble sequencing is required until after a power-on / reset

has occurred. The Start code is indicated by a <01> pattern.

This assures the MDIO line transitions from the default idle

line state. Turnaround is an idle bit time inserted between the

To avoid

contention, no device actively drives the MDIO signal during

the first bit of Turnaround during a read transaction.

The

addressed VT6103 drives MDIO with a zero for the second bit

of Turn-around and follows this with the required data. IEEE

802.3 section 22.3.4.1 shows the timing relationship between

MDC and MDIO as driven / received by the Station

Management Entity (SME) and the VT6103 (PHY) for a

typical register read access. For write transactions, the station

management entity writes data to an addressed VT6103

eliminating the requirement for MDIO Turnaround.

The

Turnaround time is filled by the management entity inserting

<10> for these two bits.

Preamble Suppression

The VT6103 supports a Preamble Suppression mode. If the

station management entity (i.e. MAC or other management

controller) determines that all PHYs in the system support

Preamble Suppression by returning a one in this bit, then the

station management entity need not generate preamble for

each management transaction. The VT6103 requires a single

initialization sequence of 32 bits of preamble following

power-up/hardware reset. This requirement is generally met

by the mandatory pull-up resistor on MDIO in conjunction

with a continuous MDC, or the management access made to

determine whether Preamble Suppression is supported. While

the VT6103 requires an initial preamble sequence of 32 bits

for management initialization, it does not require a full 32 bit

sequence between each subsequent transaction. A minimum

of one idle bit between management transactions is required as

specified in IEEE 802.3u.

PHY Address Sensing

The VT6103 can be set to respond to any of the possible 32

PHY addresses. Each VT6103 connected to a common serial

MII must have a unique address. It should be noted that while

an address selection of all zeros <00000> will result in PHY

Isolate mode, this will not effect serial management access.

The VT6103 provides five PHY address pins, the state of

which are latched into the PHYCTRL register (address 10h) at

system power-up / reset. These pins are described in the pin

descriptions section of this document.

VT6103 Datasheet(PDF) 24 Page - VIA Technologies, Inc.

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