VT6103 datasheet(28/46 Pages) VIA

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VT6103 - Fast Ethernet 10 / 100 PHY / Transceiver

Revision 1.1 April 15, 2002

-22-

Functional Description

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Clock and Data Recovery

Clock Recovery – 100 Mbps

Clock recovery is done with a PLL. If there is no valid data

present on the TP inputs, the PLL is locked to the 25 MHz

TXC Transmit Clock. When valid data is detected on the TP

inputs with the squelch circuit and when the adaptive

equalizer has settled, the PLL input is switched to the

incoming data on the TP input.

The PLL then recovers a

clock by locking onto the transitions of the incoming signal

from the twisted pair wire.

The recovered data clock

frequency is 125 MHz and is divided down to produce a 25

MHz clock that is sent to the controller interface signal RXC

Receive Clock. The PLL can reliably perform the clock and

data recovery process with up to +/-3 ns or jitter on the TP

input. The VT6103 has an internal PLL watchdog timer that

monitors the receiver PLL output frequency. If the receive

PLL output frequency deviates from the TXC frequency by

more that 3% over a 8 us interval, the device assumes that the

receive PLL has not locked onto the TP input data properly

and the PLL is reset. The PLL is reset by switching its input

from the TP input data to the TXC for a period of 200 us to

retrain it to the 25 MHz frequency from the oscillator.

Data Recovery – 100 Mbps

Data recovery is performed by latching in valid data from the

TP receiver with the recovered clock extracted by the PLL.

When invalid data is detected on the TP input, the receive data

is held low. When valid data is detected on the TP inputs, the

clock recovery block extracts a 125 MHz clock from the data

stream from the TP receiver. This 125 MHz recovered clock

is then used to latch in valid data from the TP receiver.

Clock Recovery – 10 Mbps

The clock recovery process for 10 Mbps mode is identical to

the 100 Mbps mode except, (1) the recovered clock frequency

is a 2.5 MHz nibble clock, (2) the PLL is switched from TXC

to the TP input when the squelch indicates valid data, and (3)

the PLL takes up to 12 transitions (bit times) to lock onto the

preamble, so some of the preamble data symbols are lost, but

the clock recovery block recovers enough preamble symbols

to pass at least 6 nibbles of preamble to the receive controller

interface.

Data Recovery–10Mbps

The data recovery process for 10 Mbps mode is identical to

the 100 Mbps mode.

As mentioned in the Manchester

Decoder section, the data recovery process inherently

performs decoding of Manchester encoded data from the TP

inputs.

Scrambler / Descrambler

100 Mbps Scrambler

100Base-TX requires scrambling to reduce the radiated

emissions on the twisted pair. The VT6103 scrambler takes

the encoded data from the 4B5B encoder, scrambles it per the

IEEE 802.3TP-PMD specifications, and sends it to the TP

transmitter.

10 Mbps Scrambler

A scrambler is not used in 10 Mbps mode.

100 Mbps Descrambler

The VT6103 descrambler takes the scrambled data from the

data recovery block, descrambles it per the IEEE 802.3 TP-

PMD specifications, aligns the data on the correct 5B word

boundaries, and sends it to the 4B5B decoder. The algorithm

for synchronization of the descrambler is the same as the

algorithm outlined in the IEEE802.3 TP-PMD specification.

Once the descrambler is synchronized, it will maintain

synchronization as long as enough descrambled idle pattern

1's are detected within a given interval.

To stay in

synchronization, the descrambler needs to detect at least 25

consecutive descrambled idle pattern 1's in a 1 ms interval. If

25 consecutive descrambled idle pattern 1's are not detected

within the 1 ms interval, the descrambler goes out of

synchronization and restarts the synchronization process. If

the

descrambler

the

unsynchronized

state,

the

descrambler loss of synchronization detect bit is set in the MI

Status Output register to indicate this condition. Once this bit

is set, it will stay set until the descrambler achieves

synchronization.

The output of the descrambler is also

aligned according to the 4B/5B code groups. This alignment

procedure is done by looking for the /J/K/ symbols at the

beginning of the packet and then aligning all subsequent

4B/5B words relative to the beginning of the /J/K/ symbols.

10 Mbps Descrambler

A descrambler is not used in 10 Mbps mode.

VT6103 Datasheet(PDF) 28 Page - VIA Technologies, Inc.

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