33742 datasheet(17/65 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33742

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 6. Dynamic Electrical Characteristics

Characteristics noted under conditions 4.75 V

≤ V2 ≤ 5.25 V, 5.5 V ≤ VSUP ≤ 18 V, and -40°C ≤ TA ≤ 125°C. Typical values

noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

DIGITAL INTERFACE TIMING (SCLK, CS, MOSI, MISO) (28)

SPI Operation Frequency

fREQ

0.25

—

4.0

MHz

SCLK Clock Period

tPCLK

250

—

N/A

SCLK Clock High Time

tWSCLKH

125

—

N/A

SCLK Clock Low Time

tWSCLKL

125

—

N/A

Falling Edge of CS to Rising Edge of SCLK

tLEAD

100

—

N/A

Falling Edge of SCLK to Rising Edge of CS

tLAG

100

—

N/A

MOSI to Falling Edge of SCLK

tSISU

—

N/A

Falling Edge of SCLK to MOSI

tSIH

—

N/A

MISO Rise Time (29)

CL = 220 pF

tRSO

—

MISO Fall Time (29)

CL = 220 pF

tFSO

—

Time from Falling or Rising Edges of CS

MISO Low Impedance

MISO High Impedance

tSOEN

tSODIS

—

Time from Rising Edge of SCLK to MISO Data Valid

0.2 VDD ≤ MISO ≥ 0.8 VDD, CL = 200 pF

tVALID

—

STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT)

Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)

and Stop Mode Activation (30)

tCS-STOP

—

µs

Interrupt Low-Level Duration

Stop Mode

tINT

7.0

µs

Internal Oscillator Frequency (31)

fOSC

—

100

—

kHz

Watchdog Period Normal and Standby Modes

Period 1

Period 2

Period 3

Period 4

tWDOG

8.58

39.6

308

9.75

100

350

10.92

50.4

112

392

Notes

28.

See Figure 7, SPI Timing Diagram, page 21.

29.

Not production tested. Guaranteed by design.

30.

Not production tested. Guaranteed by design. Detected by V2 OFF.

31.

fOSC is indirectly measured (1.0 ms reset) and trimmed.

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