ADATE207

Rev. 0 | Page 33 of 36

Position

Description

Reset State

Bit 10

Channel 2 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of

the timing error flags of the channel. More details of the error can be found by reading the error flags

for Channel 2.

0x0

Bit 09

Channel 1 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of

the timing error flags of the channel. More details of the error can be found by reading the error flags

for Channel 1.

0x0

Bit 08

Channel 0 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of

the timing error flags of the channel. More details of the error can be found by reading the error flags

for Channel 0.

0x0

Bit 07

Channel 3 High Comparator Output. This indicates the state of the high comparator. When high, the

Undefined

Bit 06

Channel 3 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT

Undefined

Bit 05

Channel 2 High Comparator Output. This indicates the state of the high comparator. When high, the

Undefined

Bit 04

Channel 2 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT

Undefined

Bit 03

Channel 1 High Comparator Output. This indicates the state of the high comparator. When high, the

Undefined

Bit 02

Channel 1 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT

Undefined

Bit 01

Channel 0 High Comparator Output. This indicates the state of the high comparator. When high, the

Undefined

Bit 00

Channel 0 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT

Undefined

Name:

Chip Information

Address:

0x1F

Type:

Read

Table 39. Chip Information

Position

Description

Reset State

Bits[15:00]

Reserved.

N/A