ADATE207 datasheet(15/36 Pages) AD

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ADATE207

Rev. 0 | Page 15 of 36

PER_EARLY_T0EN

PER_EARLY_C0EN

MCLK

INPUT DELAY[7:0]

T0 PIPELINE

TIMING

GENERATOR

Figure 10. INPUT_DELAY Pipeline

Figure 11 shows the timing of PER_EARLY_T0EN and

the associated period delay offset, INPUT_DELAY. The

INPUT_DELAY signal is added to each programmed delay

across all channels. This input delay can change for each

PER_EARLY_T0EN period.

The delay from the pattern inputs to the DUT is four T0

pipeline delays, plus four MCLK pipeline delays, plus

approximately 27.5 ns of analog delay, plus any programmed

delay as shown in Figure 8.

The delay from the pattern inputs to the fail outputs is eight

PER_EARLY_T0EN periods plus the programmed T0

alignment pipeline depth.

DUT CAPTURE

Each compare event can strobe the state of the dual comparators

signals for each pin. These are resynchronized to T0 periods

and output for use in mixed signal capture applications. There

are four DUT capture pins per channel, PAT_DUTDATA_x and

each can be configured to output the high or low comparators

of each of the four possible compare events.

TMU MULTIPLEXER

The ADATE207 supports time measurement via an external

time measurement unit (TMU) in the following configurations:

•

Connect the high comparator output of any pin to

TMU_ARM, TMU_START, or TMU_STOP.

•

Connect the low comparator output of any pin to

TMU_ARM, TMU_START, or TMU_STOP.

The time measurement unit select logic provides time and

frequency measurement capability from the high or low

comparator outputs of any digital pin. To accomplish this

task, independent multiplexers direct the high and low

comparator outputs of the digital pins to the time measurement

unit signals, TMU_ARM, TMU_START, and TMU_STOP. Off-

chip control logic must select the appropriate TMU bus output

signal from the ADATE207 and direct its selection to the TMU.

The TMU outputs are high speed, differential 8 mA drivers and

can be tristated for bus applications.

LOW JITTER CLOCK DRIVER

The ADATE207 has 2-to-1 multiplexers in the DR_DATA_CH3

and DR_DATA_CH2 output drivers to allow an external low

jitter clock signal to drive the DCL. This feature is not available

on the DR_DATA_CH0 and DR_DATA_CH1 outputs.

CLOCK GENERATOR MODE

The ADATE207 incorporates a clock generation mode to allow

it to be used as a programmable clock generator. In this mode, it

is possible for each of the four channels to produce an

independently programmable clock.

To activate this mode, PER_EARLY_T0EN and the

CLKGEN_MD_EN input need to be set high. In this mode,

PAT_DATA_VALID has no effect. The pattern data signals

(PAT_PATDATA_x) are interpreted as period offsets and the

PAT_MASK[x] inputs are used as period start enables. See

Table 11 for details of signal mapping. The use model for this

mode is

•

Program drive high/drive low operations at Address 0 in

the waveform memory. Depending on the delays, the value

per edge, the duty cycle, and the start level can be adjusted

per channel

•

Four different clocks can be controlled by using

PAT_MASK[N] as equivalent period start signals for an

individual Channel N.

•

Skew/insertion delay of the clocks can be adjusted

individually by using I_PAT_PATADATA_N as an

INPUT_DELAY signal for Channel N.

DEVICE RESET

The ADATE207 has an internal PLL and FIFO that require reset

upon power up and changes to the MCLK input. The device has

three reset controls.

•

RESET_B input pin for hard resets.

•

CPU writeable control bit (Bit 00 in Register 0x19) for soft

resets.

•

CPU writeable control bit (Bit 03 in Register 0x19) to reset

errors and internal FIFOs.

MCLK

PER_EARLY_T0EN

INPUT_DELAY[7:0]

DELAY

Figure 11. Timing Diagram for PER_EARLY_T0EN and INPUT_DELAY

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