ADATE207

Rev. 0 | Page 21 of 36

CONTROL AND STATUS REGISTERS

This section details the breakdown of the configuration and status registers in the ADATE207. An address map provides the locations of

all registers, and the detailed descriptions that follow show how each register is used.

Table 13. Address Map

Chip Address

Register Description

0x00

Comparator and Fail Status. Channel-specific address space.

0x01

Fail Counter Low.

0x02

Fail Counter High.

0x03

Static Configuration.

0x04

Dynamic Configuration.

0x05

Waveform/Calibration Memory Address.

0x06

Waveform D0 Vernier Delay and Action.

0x07

Waveform D0 Course Delay.

0x08

Waveform D1 Vernier Delay and Action.

0x09

Waveform D1 Course Delay.

0x0A

Waveform D2 Vernier Delay and Action.

0x0B

Waveform D2 Course Delay.

0x0C

Waveform D3 Vernier Delay and Action.

0x0D

Waveform D3 Course Delay.

0x0E

Calibration Memory D0.

0x0F

Calibration Memory D1.

0x10

Calibration Memory D2.

0x11

Calibration Memory D3.

0x12

DUT Data Selection.

0x13 to 0x18

Unused. Reserved.

0x19

Software Resets. Common register address space.

1x1A

Round Trip Delay Value.

0x1B

T0 Alignment Pipeline Depth.

0x1C

TMU Channel Select.

0x1D

Channel Multiplex Enable.

0x1E

Channel Status.

0x1F

Chip Information.