ADATE207

Rev. 0 | Page 22 of 36

CHANNEL SPECIFIC AND COMMON REGISTERS

Detailed register descriptions divided into channel-specific and common registers.

Channel Specific Registers

Name:

Comparator and Fail Status

Address:

0x00

Type:

Read

Table 14. Comparator and Fail Status

Position

Description

Reset State

Bits[15:08]

Not used.

0x00

Bit 07

Edge Error: Edges Longer Than 4 T0 Cycles. This occurs when the edge delay counters are reloaded

before they complete counting down, thus, causing a missing edge.

0x0

Bit 06

Edge Error: Out of Order Edge Strobes. This occurs when one or more edge delay counters complete

counting out of order (wrong action code is paired with an edge), or two edge delay counters complete

counting at the same CLK400 edge (causing a missing edge).

0x0

Bit 05

Edge Error: Adder Overflow. This occurs when the residue or calibration constant adders overflow

causing edge delays to wrap around. This results in incorrect edge timing.

0x0

Bit 04

Edge Error: Two Edges Too Close. This occurs when either the drive or compare verniers receive

nonincreasing delay values in back-to-back CLK400 cycles. The verniers become unsynchronized

and cause incorrect edge timing thereafter.

0x0

Bits[03:00]

Accumulated Fail Registers. These four data bits provide up to four possible DUT failures—one for each

edge delay. The bits are decoded as follows:

0x0

Bit 00 = D0 edge or window failures.

Bit 01 = D1 edge failure or D0/D1 window failures.

Bit 02 = D2 edge or window failures.

Bit 03 = D3 edge failure or a D3/D2 window failure.

Name:

Fail Counter Low

Address:

0x01

Type:

Read/Write

Table 15. Fail Counter Low

Position

Description

Reset State

Bits[15:00]

Fail Counter Data Low Order Bits. This field contains the 16 LSBs of the fail counter. This register and the

fail counter data high register represent a binary encoded, 32-bit, number of fail events (up to 4 fail events

per T0 period) detected during the last pattern burst.

The CPU reads this register while the pattern is bursting, capturing a snapshot of the fail count at the time

of reading the low register. Writes during pattern burst can produce indeterminate results if fails are

occurring during the write cycle.

The CPU must read the contents of the counter by performing sequential reads from the fail counter low

register followed by a read from the fail counter high register. Reading from the fail counter low register

performs the transfer of data from the counter to a temporary holding register. Reading from the fail

counter high register reads solely from the temporary holding register.

For diagnostics, the CPU can preload the contents of the counter by performing sequential writes to the

Fail Counter CHx data low register followed by a write to the Fail Counter Chx data high register. Writing to

the Fail Counter Chx data high register performs the transfer of data from temporary holding registers to

the 32-bit counter.

0x0000