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ADATE207

Rev. 0 | Page 13 of 36

2.5

2.0

1.5

1.0

0.5

TYPICAL VERNIER

DELAY CODE

Figure 7. Delay Curve of a Typical Vernier

DRIVE AND COMPARE LOGIC

The drive logic consists of two high speed differential reset/set

flip flops controlling the drive data and drive enable signals.

They are controlled from the four events per channel, enabled

via decode of the event code. In addition, the flip flops can be

controlled from an adjacent channel event in a multiplex mode.

The four-channel device can be multiplexed such that there are

either four pins with four events each, or two pins with eight

events each.

The compare logic supports dual level comparators for voltage

comparisons against VOL and VOH levels. The comparator outputs

are checked against four possible states, low (less than VOL), high

(greater than VOH), off or midband (between VOL and VOH), and

valid (either above VOH or below VOL). The high comparator

inputs (COMP_H) are Logic 1 when the DUT output is greater

than VOH. The low comparator inputs (COMP_L) are Logic 1

when the DUT output is greater than VOL.

The compare logic supports both single edge and window com-

parisons and can support up to four comparisons per cycle using

the four events. Each comparison can generate a fail, accumulating

per pin with individual fail counters. Fail outputs are resynchro-

nized to T0 and output for fail processing.

Fails can be masked on a per edge basis and match mode is

supported. Masking of failures prevents incrementing of the fail

counter and the setting of the accumulated fail registers. It does

not prevent the fail signals from reflecting the comparison state

of the expect edge. Strobe comparison fails are associated with

the timing edge that generates the strobe.

A pair of timing edges can be used to create a window of time

over which to check the DUT output levels. Timing Edge D0

and Timing Edge D1 form a window with D0 opening the

window and D1 closing the window. Timing Edge D2 and

Timing Edge D3 are similarly employed for window

comparisons. Window comparison fails are associated with the

timing edge that generates the window close strobe. Window

failures only come out on D1 or D3 edges. Table 9 shows the

relationship between the edges on which the fails are detected

and the bit position on the PAT_FAIL pins.

Table 9. Edge and Window Fail Bit Descriptions

Bit

Fail1

Description

Fail

Mask Bit

PAT_FAIL_x[3]

Edge D3 Fail and Window

D2/D3 Fail

PAT_MASK[3]

PAT_FAIL_x[2]

Edge D2 Fail

PAT_MASK[2]

PAT_FAIL_x[1]

Edge D1 Fail and Window

D0/D1 Fail

PAT_MASK[1]

PAT_FAIL_x[0]

Edge D0 Fail

PAT_MASK[0]

1 PAT_FAIL_x refers to Channel 0 to Channel 3

PAT_MASK inputs mask failures across the channels for four

possible edges. Asserting PAT_MASK[0] masks failures for

Timing Edge D0. When failures are masked, the accumulated fail

PAT_FAIL_x outputs remain asserted if the expected vector is

not seen allowing for match mode applications.

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