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DSP56300FM/AD Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc |
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DSP56300FM/AD Datasheet(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 64 page ![]() Maximum Ratings DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 25 4.11 JTAG/OnCE Interface 5 Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (e.g., either GND or VDD). The suggested value for a pullup or pulldown resistor is 4.7 k Ω. PLOCK Output PLOCK—When this pin is configured as a PLL lock pin, this signal is asserted high when the on-chip PLL enabled and locked and de-asserted when the PLL enabled and unlocked. This pin is also asserted high when the PLL is disabled. Internal Pull down resistor. This input is 5 V tolerant Table 14. JTAG/OnCE Interface Signal Name Signal Type State during Reset Signal Description TCK Input Input Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. Internal Pull up resistor. This input is 5 V tolerant. TDI Input Input Test Data Input—TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. TDO Output Tri-stated Test Data Output—TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. TMS Input Input Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK. Internal Pull up resistor. This input is 5 V tolerant. Table 13. Timer Signal (continued) Signal Name Type State during Reset Signal Description |
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