DSP56300FMSLASHAD datasheet(44/64 Pages) FREESCALE

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DSP56374 Data Sheet, Rev. 4.2

Enhanced Serial Audio Interface Timing

Freescale Semiconductor

Figure 11. I2C Timing

Enhanced Serial Audio Interface Timing

Table 24. Enhanced Serial Audio Interface Timing

No.

Characteristics1, 2, 3

Symbol

Expression3

Min

Max

Condition4

Unit

Clock cycle5

tSSICC

× Tc

26.4

—

x ck

i ck

Clock high period

• For internal clock

tSSICCH

× Tc − 0.5

12.8

—

• For external clock

× Tc

13.4

—

Clock low period

• For internal clock

tSSICCL

× Tc

13.4

—

• For external clock

× Tc

13.4

—

SCKR edge to FSR out (bl) high

—

17.0

7.0

x ck

i ck a

SCKR edge to FSR out (bl) low

—

17.0

7.0

x ck

i ck a

SCKR edge to FSR out (wr) high6

——

—

19.0

9.0

x ck

i ck a

SCKR edge to FSR out (wr) low6

——

—

19.0

9.0

x ck

i ck a

SCKR edge to FSR out (wl) high

—

16.0

6.0

x ck

i ck a

Start

SCL

HREQ

SDA

ACK

MSB

LSB

Stop

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