DSP56300FMSLASHAD datasheet(37/64 Pages) FREESCALE

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Serial Host Interface SPI Protocol Timing

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

SCK edge following the first SCK

sampling edge to HREQ output

deassertion

Slave

Bypassed

3.0 x TC + 30

—

Very Narrow

3.0 x TC + 40

—

Narrow

3.0 x TC + 80

100

—

Wide

3.0 x TC + 120

150

—

Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

4.0 x TC

57.0

—

Very Narrow

4.0 x TC

67.0

—

Narrow

4.0 x TC

107.0

—

Wide

4.0 x TC

157.0

—

SS deassertion to HREQ output not

deasserted (CPHA = 0)

Slave

—

3.0 x TC + 30

50.0

—

SS deassertion pulse width (CPHA = 0)

Slave

—

2.0 x TC

13.4

—

HREQ in assertion to first SCK edge

Master

Bypassed

0.5 x TSPICC +

3.0 x TC + 5

—

Very Narrow

0.5 x TSPICC +

3.0 x TC + 5

—

Narrow

0.5 x TSPICC +

3.0 x TC + 5

125

—

Wide

0.5 x TSPICC +

3.0 x TC + 5

225

—

HREQ in deassertion to last SCK

sampling edge (HREQ in set-up time)

(CPHA = 1)

Master

—

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

HREQ assertion width

Master

—

3.0 x TC

—

Note:

1 V

CORE_VDD = 1.2 5 ± 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF

2 Periodically sampled, not 100% tested

3 All times assume noise free inputs.

4 All times assume internal clock frequency of 150 MHz.

5 Equation applies when the result is positive T

Table 21. Serial Host Interface SPI Protocol Timing (continued)

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

DSP56300FM/AD Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc

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