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DSP56300FM/AD Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc |
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DSP56300FM/AD Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc |
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42 / 64 page  DSP56374 Data Sheet, Rev. 4.2 Serial Host Interface (SHI) I2C Protocol Timing Freescale Semiconductor 42 47 Start condition hold time THD;STA 4.0 — 0.6 — µs 48 SCL low period TLOW 4.7 — 1.3 — µs 49 SCL high period THIGH 4.0 — 1.3 — µs 50 SCL and SDA rise time TR —5.0 — 5.0 ns 51 SCL and SDA fall time TF —5.0 — 5.0 ns 52 Data set-up time TSU;DAT 250 — 100 — ns 53 Data hold time THD;DAT 0.0 — 0.0 0.9 µs 54 DSP clock frequency • Filters bypassed • Very Narrrow filters enabled • Narrow filters enabled • Wide filters enabled FOSC 10.6 10.6 11.8 13.1 — — — — 28.5 28.5 39.7 61.0 — — — — MHz MHz MHz MHz 55 SCL low to data out valid TVD;DAT —3.4 — 0.9 µs 56 Stop condition setup time TSU;STO 4.0 — 0.6 — µs 57 HREQ in deassertion to last SCL edge (HREQ in set-up time) tSU;RQI 0.0 — 0.0 — ns 58 First SCL sampling edge to HREQ output deassertion2 • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled TNG;RQO 4 × T C + 30 4 × T C + 50 4 × T C + 130 4 × T C + 230 — — — — 57.0 77.0 157.0 257.0 — — — — 57.0 67.0 157.0 257.0 ns ns ns ns 59 Last SCL edge to HREQ output not deasserted2 • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled TAS;RQO 2 × T C + 30 2 × T C + 40 2 × T C + 80 2 × T C + 130 44 54 94 144 — — — — 44 54 94 144 — — — — ns ns ns ns 60 HREQ in assertion to first SCL edge • Filters bypassed • Very Narrow filters enabled • Narrow filters enabled • Wide filters enabled TAS;RQI 4327 4317 4282 4227 — — — — 927 917 877 827 — — — — ns ns ns ns 61 First SCL edge to HREQ is not asserted (HREQ in hold time.) tHO;RQI 0.0 — 0.0 — ns Table 22. SHI I2C Protocol Timing (continued) Standard I2C No. Characteristics1,2,3,4,5 Symbol/ Expression Standard Fast-Mode Unit Min Max Min Max |
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