DSP56300FMSLASHAD datasheet(11/64 Pages) FREESCALE

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Signal Groupings

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

MOSI

Input or output

Tri-stated

SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI

is the master data output line. The MOSI signal is used in conjunction with

the MISO signal for transmitting and receiving serial data. MOSI is the slave

data input line when the SPI is configured as a slave. This signal is a

Schmitt-trigger input when configured for the SPI Slave mode.

HA0

Input

I2C Slave Address 0—This signal uses a Schmitt-trigger input when

configured for the I2C mode. When configured for I2C slave mode, the HA0

signal is used to form the slave device address. HA0 is ignored when

configured for the I2C master mode.

This signal is tri-stated during hardware, software, and individual reset.

Thus, there is no need for an external pull-up in this state.

This pin has an internal pull up resistor.

This input is 5 V tolerant.

Input

Ignored Input SPI Slave Select—This signal is an active low Schmitt-trigger input when

configured for the SPI mode. When configured for the SPI Slave mode, this

signal is used to enable the SPI slave for transfer. When configured for the

SPI master mode, this signal should be kept de-asserted (pulled high). If it

is asserted while configured as SPI master, a bus error condition is flagged.

If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO

output signal in the high-impedance state.

HA2

Input

I2C Slave Address 2—This signal uses a Schmitt-trigger input when

configured for the I2C mode. When configured for the I2C Slave mode, the

HA2 signal is used to form the slave device address. HA2 is ignored in the

I2C master mode.

This pin has an internal pull up resistor.

This input is 5 V tolerant.

HREQ

PH4

Input or Output

Input, output, or

disconnected

Tri-stated

Host Request—This signal is an active low Schmitt-trigger input when

configured for the master mode but an active low output when configured for

the slave mode.

When configured for the slave mode, HREQ is asserted to indicate that the

SHI is ready for the next data word transfer and de-asserted at the first clock

pulse of the new data word transfer. When configured for the master mode,

HREQ is an input. When asserted by the external slave device, it will trigger

the start of the data word transfer by the master. After finishing the data word

transfer, the master will await the next assertion of HREQ to proceed to the

next transfer. This pin can also be programmed as GPIO.

Port H4—When HREQ is configured as GPIO, this signal is individually

programmable as input, output, or internally disconnected.

This pin has an internal pull up resistor.

This input is 5 V tolerant.

Table 9. Serial Host Interface Signals (continued)

Signal

Name

Signal Type

State during

Reset

Signal Description

DSP56300FM/AD Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc

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