DSP56300FMSLASHAD datasheet(32/64 Pages) FREESCALE

32 / 64 page

DSP56374 Data Sheet, Rev. 4.2

Reset, Stop, Mode Select, and Interrupt Timing

Freescale Semiconductor

Reset, Stop, Mode Select, and Interrupt Timing

Table 20. Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

Min

Max

Unit

Delay from RESET assertion to all pins at reset

value3

—

Required RESET duration4

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

2 xTC

13.4

—

2 x TC

13.4

—

Syn reset deassert delay time

•Minimum

× TC

13.4

—

• Maximum (PLL enabled)

(2xTC)+TLOCK

5.0

—

Mode select setup time

10.0

—

Mode select hold time

10.0

—

Minimum edge-triggered interrupt request assertion

width

2 xTC

13.4

—

Minimum edge-triggered interrupt request

deassertion width

2 xTC

13.4

—

Delay from interrupt trigger to interrupt code

execution

10 × TC + 5

—

Duration of level sensitive IRQA assertion to ensure

interrupt service (when exiting Stop)1, 2, 3

• PLL is active during Stop and Stop delay is

enabled

(OMR Bit 6 = 0)

9+(128× TC)

854

—

µs

• PLL is active during Stop and Stop delay is not

enabled

(OMR Bit 6 = 1)

× TC

165

—

• PLL is not active during Stop and Stop delay is

enabled (OMR Bit 6 = 0)

9+(128xTC) + TLOCK

5.7

• PLL is not active during Stop and Stop delay is

not enabled (OMR Bit 6 = 1)

(25 x TC) + TLOCK

5ms

• Delay from IRQA, IRQB, IRQC, IRQD, NMI

assertion to general-purpose transfer output

valid caused by first interrupt instruction

execution1

10 x TC + 3.0

69.0

DSP56300FM/AD Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

DSP56300FM/AD Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL