DSP56300FMSLASHAD datasheet(43/64 Pages) FREESCALE

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Programming the Serial Clock

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

Programming the Serial Clock

The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the

HCKR (SHI clock control register).

The expression for TI2CCP is

TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

Eqn. 1

where

— HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00

to $FF) may be selected.

In I2C mode, the user may select a value for the programmed serial clock cycle from

× TC (if HDM[7:0] = $02 and HRS = 1)

Eqn. 2

4096

× TC (if HDM[7:0] = $FF and HRS = 0)

Eqn. 3

The programmed serial clock cycle (TI2CCP) should be chosen in order to achieve the desired SCL serial

clock cycle (TSCL), as shown in Table 23.

Note:

1 V

CORE_VDD = 1.2 5 ± 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF

2 Pull-up resistor: R P (min) = 1.5 kOhm

3 Capacitive load: C b (max) = 50 pF

4 All times assume noise free inputs

5 All times assume internal clock frequency of 150MHz

Table 23. SCL Serial Clock Cycle (TSCL) Generated as Master

Nominal

TI2CCP + 3 × TC + 45ns + TR

Table 22. SHI I2C Protocol Timing (continued)

Standard I2C

No.

Characteristics1,2,3,4,5

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

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