DSP56300FMSLASHAD datasheet(51/64 Pages) FREESCALE

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JTAG Timing

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

Figure 18. Test Clock Input Timing Diagram

109

TCK cycle time in Crystal mode

100.0

—

110

TCK clock pulse width measured at 1.65 V

50.0

—

111

TCK rise and fall times

—

3.0

112

Boundary scan input data setup time

15.0

—

113

Boundary scan input data hold time

24.0

—

114

TCK low to output data valid

—

40.0

115

TCK low to output high impedance

—

40.0

116

TMS, TDI data setup time

5.0

—

117

TMS, TDI data hold time

25.0

—

118

TCK low to TDO data valid

—

44.0

119

TCK low to TDO high impedance

—

44.0

Note:

1. VCORE_VDD = 1.25 V ± 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

Table 27. JTAG Timing (continued)

No.

Characteristics

All frequencies

Unit

Min

Max

TCK

(Input)

VIH

VIL

109

110

111

DSP56300FM/AD Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

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