XRT83SL314 datasheet(23/83 Pages) EXAR

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XRT83SL314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.1

2.6

Clock and Data Recovery

The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the

incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-

channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an

incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered

data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To

update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 9 is a

timing diagram of the receive data updated on the rising edge of RCLK. Figure 10 is a timing diagram of the

receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 5.

FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK

FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK

RCL K

RP O S

RNE G

RCL K

RCLK

RPOS

RNEG

RCLK

XRT83SL314 Datasheet(PDF) 23 Page - Exar Corporation