XRT83SL314 datasheet(46/83 Pages) EXAR

46 / 83 page

XRT83SL314

REV. 1.0.1

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

5.1

The Microprocessor Interface Block Signals

The LIU may be configured into different operating modes and have its performance monitored by software

through a standard microprocessor using data, address and control signals.

These interface signals are

described below in Table 15, Table 16, and Table 17. The microprocessor interface can be configured to

operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some

of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when

the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as

required by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous

processor, see Figure 41 and Table 20) Table 15 lists and describes those microprocessor interface signals

whose role is constant across the two modes. Table 16 describes the role of some of these signals when the

microprocessor interface is operating in the Intel mode. Likewise, Table 17 describes the role of these signals

when the microprocessor interface is operating in the Motorola Power PC mode.

TABLE 15: XRT84L314 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL

AND

MOTOROLA MODES

PIN NAME

TYPE

DESCRIPTION

µPTS[2:0]

Microprocessor Interface Mode Select Input pins

These three pins are used to specify the microprocessor interface mode. The relationship

between the state of these three input pins, and the corresponding microprocessor mode is

presented in Table 14.

DATA[7:0]

I/O

Bi-Directional Data Bus for register "Read" or "Write" Operations.

ADDR[10:8]

Three-Bit Address Bus Inputs

The 3 MSBs of the address bits are used as a chip select decoder. The state of these 3 pins

enable the Chip Selects for additional LIU devices.

NOTE: See the 84-Channel Application Section of this datasheet.

ADDR[7:0]

Eight-Bit Address Bus Inputs

The XRT83SL314 LIU microprocessor interface uses a direct address bus. This address bus

is provided to permit the user to select an on-chip register for Read/Write access.

Chip Select Input

This active low signal selects the microprocessor interface of the XRT83SL314 LIU and

enables Read/Write operations with the on-chip register locations.

TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS

XRT83SL314

PIN NAME

INTEL

EQUIVALENT PIN

TYPE

DESCRIPTION

ALE_TS

ALE

Address-Latch Enable: This active high signal is used to latch the contents on

the address bus ADDR[7:0]. The contents of the address bus are latched into the

ADDR[7:0] inputs on the falling edge of ALE.

RD_WE

Read Signal: This active low input functions as the read signal from the local

µP.

When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read oper-

ation has been requested and begins the process of the read cycle.

WR_R/W

Write Signal: This active low input functions as the write signal from the local

µP.

When this pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write

operation has been requested and begins the process of the write cycle.

RDY_TA

RDY

Ready Output: This active low signal is provided by the LIU device. It indicates

that the current read or write cycle is complete, and the LIU is waiting for the next

command.

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