AM3359 datasheet(150/256 Pages) TI1

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AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351

SPRS717L – OCTOBER 2011 – REVISED MARCH 2020

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Peripheral Information and Timings

7.7.2.1.2.2 Compatible JEDEC LPDDR Devices

Table 7-34 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.

Generally, the LPDDR interface is compatible with x16 LPDDR400 speed grade LPDDR devices.

Table 7-34. Compatible JEDEC LPDDR Devices (Per Interface)(1)

NO.

PARAMETER

MIN

MAX

UNIT

JEDEC LPDDR device speed grade

LPDDR400

JEDEC LPDDR device bit width

x16

Bits

JEDEC LPDDR device count

Devices

JEDEC LPDDR device terminal count

Terminals

(1) If the LPDDR interface is operated with a clock frequency less than 200 MHz, lower-speed grade LPDDR devices may be used if the

minimum clock period specified for the LPDDR device is less than or equal to the minimum clock period selected for the AM335x

LPDDR interface.

7.7.2.1.2.3 PCB Stackup

The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-

35. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal

integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.

Table 7-35. Minimum PCB Stackup(1)

LAYER

TYPE

DESCRIPTION

Signal

Top signal routing

Plane

Ground

Plane

Split Power Plane

Signal

Bottom signal routing

(1) All signals that have critical signal integrity requirements should be routed first on layer 1. It may not be possible to route all of these

signals on layer 1, therefore requiring routing of some signals on layer 4. When this is done, the signal routes on layer 4 must not cross

splits in the power plane.

AM3359 Datasheet(PDF) 150 Page - Texas Instruments

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