H838024 datasheet(166/697 Pages) RENESAS

166 / 697 page

Section 5 Power-Down Modes

Rev. 7.00 Mar 10, 2005 page 124 of 652

REJ09B0042-0700

Bit 3—Low Speed on Flag (LSON)

This bit chooses the system clock (

φ) or subclock (φ

SUB) as the CPU operating clock when watch

mode is cleared. The resulting operation mode depends on the combination of other control bits

and interrupt input.

Bit 3

LSON

Description

The CPU operates on the system clock (

φ)

(initial value)

The CPU operates on the subclock (

SUB)

Bit 2—Reserved

Bit 2 is reserved: it is always read as 1 and cannot be modified.

Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)

Bits 1 and 0 choose

osc/128,

osc/64,

osc/32, or

osc/16 as the operating clock in active (medium-

speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-

speed) mode or subactive mode.

Bit 1

MA1

Bit 0

MA0

Description

osc/16

osc/32

osc/64

osc/128

(initial value)

System Control Register 2 (SYSCR2)

Bit

Initial value

Read/Write



NESEL

R/W

DTON

R/W

SA0

R/W

MSON

R/W

SA1

R/W

SYSCR2 is an 8-bit read/write register for power-down mode control.

Bits 7 to 5—Reserved

These bits are reserved; they are always read as 1, and cannot be modified.

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