H838024 datasheet(211/697 Pages) RENESAS

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Section 6 ROM

Rev. 7.00 Mar 10, 2005 page 169 of 652

REJ09B0042-0700

reprogramming data computation according to table 6.10, and additional programming data

computation according to table 6.11.

4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or

additional-programming data area to the flash memory. The program address and 128-byte

data are latched in the flash memory. The lower 8 bits of the start address in the flash memory

destination area must be H'00 or H'80.

Do not use RTS instruction from data transfer to setting P bit to 1. (This does not apply to the

HD64F38124 and HD64F38122.)

5. The time during which the P bit is set to 1 is the programming time. Figure 6.12 shows the

allowable programming times.

6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

An overflow cycle of approximately 6.6 ms is allowed.

7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit

is b'0. Verify data can be read in word size from the address to which a dummy write was

performed.

Do not use RTS instruction from dummy write to verify data read. (This does not apply to the

HD64F38124 and HD64F38122.)

8. The maximum number of repetitions of the program/program-verify sequence of the same bit

is 1,000.

H838024 Datasheet(PDF) 211 Page - Renesas Technology Corp