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H838024 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 697 page  Section 6 ROM Rev. 7.00 Mar 10, 2005 page 173 of 652 REJ09B0042-0700 Erase start Set EBR Enable WDT Wait 1 µs Wait 100 µs SWE bit ← 1 n ← 1 ESU bit ← 1 E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 Wait 10 µs Disable WDT Read verify data Increment address Verify data = all 1s ? Last address of block ? All erase block erased ? Set block start address as verify address H'FF dummy write to verify address Wait 20 µs Wait 2 µs EV bit ← 1 Wait 100 µs End of erasing SWE bit ← 0 Wait 4 µs EV bit ← 0 n ≤100 ? Wait 100 µs Erase failure SWE bit ← 0 Wait 4 µs EV bit ← 0 n ← n + 1 Yes No Yes Yes Yes No No No Figure 6.11 Erase/Erase-Verify Flowchart |
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