PM5366 datasheet(164/267 Pages) PMC

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PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

152

Restrictions on frame alignment pulses only exist when TVTs are supported.

The nature of the constraints depends on whether the VT pointer processors

(VTPPs) are bypassed:

• If the Egress VTPP is bypassed, the SAC1FP pulse must be

precisely 13 SREFCLK cycles before the LAC1 pulse.

• If the Egress VTPP is not bypassed, the SAC1FP pulse must be 3n

- 1 (where n = 0,1,2…) SREFCLK cycles before the LAC1 pulse.

• If the Ingress VTPP is bypassed, the LDC1J1V1 pulse must be

precisely four SREFCLK cycles before the SDC1FP pulse.

• If the Ingress VTPP is not bypassed, there is no restriction on the

alignment of SDC1FP and LDC1J1V1.

12.2.2 SBI and Telecom Buses Both 77.76 MHz

The rising edge of LREFCLK must be aligned with a tolerance of +/- 5ns to the

rising edge of SREFCLK.

For reliable operation, the STM-1s used within the SBI and Telecom buses must

be aligned in time. To this end, one may manipulate the LSTM[1:0] and

SSTM[1:0] register bits and the position of the LAC1 and SDC1FP pulses. Table

15 summarizes the combinations.

Table 15

- 77.76 SBI and Telecom Bus Alignment Options

Clock Cycles LAC1 leads SDC1FP (n = 0, 1 , 2…)

LSTM[1:0]

SSTM[1:0]

4n.

4n + 1

4n + 2

4n + 3

4n + 1

4n + 2

4n + 3

4n + 1

4n + 2

4n + 3

As an alternate formulation, if SSTM[1:0] and LSTM[1:0] were converted to their

decimal equivalents, one would have to satisfy the constraint:

(LSTM – SSTM) mod 4

= (Clock Cycles LAC1 leads SDC1FP) mod 4

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