PM5366 datasheet(168/267 Pages) PMC

168 / 267 page

PRELIMINARY

PM5366 TEMAP-84

DATASHEET

PMC-2010672

ISSUE 1

HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER

AND M13 MULTIPLEXER

PROPRIETARY AND CONFIDENTIAL

156

Count registers respectively. The path maintenance datalink signal is

extracted by theDS3 RDLC HDLC receiver (if enabled).

12.4 Servicing Interrupts

The TEMAP-84 will assert INTB to logic 0 when a condition which is configured

to produce an interrupt occurs. To find which condition caused this interrupt to

occur, the procedure outlined below should be followed:

1. Read the bits of the TEMAP-84 Master Interrupt Source register (0x0010) to

identify which of the 14 interrupt registers (0x0011-0x001E) needs to be read

to identify the interrupt. For example, a logic one read in the DS3E3INT

Interrupt Source DS3/E3 registers produced the interrupt.

2. Read the bits of the second level Master Interrupt Source register to identify

the interrupt source.

3. Service the interrupt by reading the register containing the interrupt status bit

that is asserted.

4. If the INTB pin is still logic 0, then there are still interrupts to be serviced.

Otherwise, all interrupts have been serviced. Wait for the next assertion of

INTB

12.5 Using the Performance Monitoring Features

The counters in the DS3 PMON block has been sized as not to saturate if polled

every second. The T1/E1 PMON event counters are of sufficient length so that

the probability of counter saturation over a one second interval is very small (less

than 0.001%).

An accumulation interval is initiated by writing to one of the PMON event counter

initiating an accumulation interval, 3.5 recovered clock periods (RCLK for the

DS3 PMON) must be allowed to elapse to permit the PMON counter values to be

properly transferred before the PMON registers may be read.

The odds of any one of the T1/E1 counters saturating during a one second

sampling interval go up as the bit error rate (BER) increases. At some point, the

probability of counter saturation reaches 50%. This point varies, depending

upon the framing format and the type of event being counted. The BER at which

the probability of counter saturation reaches 50% is shown for various counters

in Table 18 for E1 mode, and in Table 19 for T1 mode.

PM5366 Datasheet(PDF) 168 Page - PMC-Sierra, Inc