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6.10.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuitries (PLLs) by internal regulators that derive power from the

off-chip power-supply.

There are total of three PLLs in the device in WKUP and MCU domains:

• MCU_PLL0 (MCU R5FSS PLL) with WKUP_PLLCTRL0

• MCU_PLL1 (MCU PERIPHERAL PLL)

• MCU_PLL2 (MCU CPSW PLL)

There are total of twenty PLLs in the device in MAIN domain:

• PLL0 (MAIN PLL) with PLLCTRL0

• PLL1 (PER0 PLL)

• PLL2 (PER1 PLL)

• PLL3 (CPSW9G PLL)

• PLL4 (AUDIO0 PLL)

• PLL5 (VIDEO PLL)

• PLL6 (GPU PLL)

• PLL7 (C7x PLL)

• PLL8 (ARM0 PLL)

• PLL12 (DDR PLL)

• PLL13 (C66 PLL)

• PLL14 (R5F PLL)

• PLL15 (AUDIO1 PLL)

• PLL16 (DSS PLL0)

• PLL17 (DSS PLL1)

• PLL18 (DSS PLL2)

• PLL19 (DSS PLL3)

• PLL23 (DSS PLL7)

• PLL24 (MLB PLL)

• PLL25 (VISION PLL)

Note

For more information, see:

• Device Configuration / Clocking / PLLs section in the device TRM.

• Peripherals / Display Subsystem Overview section in the device TRM.

Note

The input reference clock (OSC1_XI/OSC1_XO) is specified and the lock time is ensured by the PLL

controller, as documented in the Device Configuration chapter in the device TRM.

6.10.4.4 Module and Peripheral Clocks Frequencies

Section 6.10.5, Peripherals section documents the maximum frequency associated with the peripheral clocks of

the device.

For more details on the clocking structure of each module, reference Device Configurations chapter in the device

TRM.

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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