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Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII), and the Management Data

Input/Output (MDIO) interface for physical layer device (PHY) management.

For more information, see Gigabit Ethernet Switch (CPSW0) section in Peripherals chapter in the device TRM.

7.4.5.5 CPSW9G

The 9-port Gigabit Ethernet Switch (CPSW0) subsystem provides Ethernet packet communication for the device

and can be configured as an Ethernet switch. CPSW0 features the Serial Gigabit Media Independent Interface

(SGMII), Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent Interface (RMII)

and the Management Data Input/Output (MDIO) interface for physical layer device (PHY) management.

For more information, see Gigabit Ethernet Switch (MCU_CPSW0) section in Peripherals chapter in the device

TRM.

7.4.5.6 DCC

The Dual Clock Comparator (DCC) is used to determine the accuracy of a clock signal during the time

execution of an application. Specifically, the DCC is designed to detect drifts from the expected clock frequency.

The desired accuracy can be programed based on calculation for each application. The DCC measures the

frequency of a selectable clock source using another input clock as a reference.

For more information, see Dual Clock Comparator (DCC) section in Peripherals chapter in the device TRM.

7.4.5.7 DDRSS

The DDR subsystem in this device comprises DDR controller, DDR PHY and wrapper logic to integrate these

blocks in the device. The DDR subsystem is referred to as DDRSS0 and is used to provide an interface to

external SDRAM devices which can be utilized for storing program or data. DDRSS0 is accessed via MSMC,

and not directly through the system interconnect.

For more information, see DDR Subsystem (DDRSS) section in Peripherals chapter in the device TRM.

7.4.5.8 DSS

The DSS is a flexible composition-enabled display subsystem, that supports multiple high resolution display

outputs. It consists of one Display Controller (DISPC) and one Frame Buffer Decompression Core (FBDC).

The DISPC supports a multi-layer blending and transparency for each of its display outputs. The DISPC also

supports a write-back pipeline with scaling to enable memory-to-memory composition and/or to capture a display

output for Ethernet video encoding.

For more information, see Display Subsystem (DSS) section in Peripherals chapter in the device TRM.

7.4.5.8.1 DSI

The MIPI DSI v1.3.1 Controller (DSITX) implements the stream arbitration and low-level protocol layer

functionalities required by MIPI DSI 1.3 standard. It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single-

link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes). The accompaning DSI

(Physical Layer) D-PHY module (DPHYTX) provides the video output interfacing by implementing a four-lane

MIPI D-PHY transmitter.

For more information, see Display Subsystem (DSS) and Display Peripherals section in Peripherals chapter in

the device TRM.

7.4.5.8.2 eDP

The VESA DP1.4/eDP1.4 Compliant Transmitter Host Controller (EDP) can output up to 4 video streams

(through Multiple Stream Transport / MST) and one audio stream through the 4-lane accompaning SerDes

module. It provides up to 25.92 Gbps of application bandwidth. An additional eDP (Physical Layer) auxiliary PHY

(AUXPHY) module implements a doubly-terminated differential pair required for 1 Mbps data rates over a long

(15m) cable.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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