TDA4VM21 datasheet(302/331 Pages) TI

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The WKUP_I2C0, MCU_I2C0, I2C0, and I2C1 controllers have dedicated I2C compliant open drain buffers, and

support high speed mode (up to 3.4 Mbps in 1.8 V mode and up to 400 kbps in 3.3 V mode). The MCU_I2C1,

I2C2, I2C3, I2C4, I2C5, and I2C6 controllers are multiplexed with standard LVCMOS I/O, connected to emulate

open drain, and support fast mode (up to 400 kbps in 1.8 V/3.3 V mode). The I2C emulation is achieved by

configuring the LVCMOS buffers to output Hi-Z instead of driving high when transmitting logic 1.

For more information, see Inter-Integrated Circuit (I2C) Interface section in Peripherals chapter in the device

TRM.

7.4.5.19 I3C

The device contains three Improved Inter-Integrated Circuit (I3C) controllers each of which provides an interface

between a local host (LH), such as an Arm, and any I3C-bus-compatible device that connects via the I3C serial

bus.

For more information, see Improved Inter-Integrated Circuit (I3C) Interface section in Peripherals chapter in the

device TRM.

7.4.5.20 MCAN

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed

real-time control. CAN has high immunity to electrical interference. In a CAN network, many short messages are

broadcast to the entire network, which provides for data consistency in every node of the system.

The MCAN module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate) specifications. CAN

FD feature allows high throughput and increased payload per data frame. The classic CAN and CAN FD devices

can coexist on the same network without any conflict.

For more information, see Modular Controller Area Network (MCAN) section in Peripherals chapter in the device

TRM.

7.4.5.21 MCASP

The MCASP functions as a general-purpose audio serial port are optimized to the requirements of various audio

applications. The MCASP module can operate in both transmit and receive modes. The MCASP is useful for

time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and transmission as well as

for an inter-component digital audio interface transmission (DIT). The MCASP has the flexibility to gluelessly

connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer component.

Although inter-component digital audio interface reception (DIR) mode (this is, S/PDIF stream receiving) is not

natively supported by the MCASP module, a specific TDM mode implementation for the MCASP receivers allows

an easy connection to external DIR components (for example, S/PDIF to I2S format converters).

For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device

TRM.

7.4.5.22 MCRC Controller

VBUSM CRC controller is a module which is used to perform CRC (Cyclic Redundancy Check) to verify the

integrity of a memory system. A signature representing the contents of the memory is obtained when the

contents of the memory are read into MCRC Controller. The responsibility of MCRC controller is to calculate

the signature for a set of data and then compare the calculated signature value against a predetermined good

signature value. MCRC controller provides four channels to perform CRC calculation on multiple memories in

parallel and can be used on any memory system. Channel 1 can also be put into data trace mode, where MCRC

controller compresses each data being read through CPU read data bus.

For more information, see MCRC Controller section in Interprocessor Communication chapter in the device

TRM.

7.4.5.23 MCSPI

The MCSPI module is a multichannel transmit/receive, master/slave synchronous serial bus.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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