TDA4VM21 datasheet(304/331 Pages) TI

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7.4.5.29 Timers

All timers include specific functions to generate accurate tick interrupts to the operating system.

Each timer can be clocked from several different independent clocks. The selection of clock source is made from

registers in the MCU_CTRL_MMR0/CTRL_MMR0.

In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer

PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0

through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each

MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[1-0] PWM output.

In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM

outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances.

System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0]

source for each TIMER_IO[7-0] PWM output.

Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous

even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be

cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.

When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit

prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at

the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.

For more information, see Timers section in Peripherals chapter in the device TRM.

7.4.5.30 UART

The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There

are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function

clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral

devices or interprocessor communication between devices.

For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in

Peripherals chapter in the device TRM.

7.4.5.31 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange

between a host device and a wide range of simultaneously accessible peripherals.

The device supports two identical USB subsystems:

• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY

and HS/FS/LS (1) (USB2.0) PHY

• USB3SS1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY

and HS/FS/LS (USB2.0) PHY

For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device

TRM.

7.4.5.32 UFS

The Universal Flash Storage (UFS) interface is a standard-based serial interface engine.

There is one UFS module inside the device - UFS0. The UFS module includes one UFS 2.1 host controller (HC)

with an integrated M-PHY.

The UFS module complies with the standards as listed in Table 7-1.

Table 7-1. UFS Standards

DOCUMENT

VERSION

DESCRIPTION

JESD220-1A

v1.1

Universal Flash Storage (UFS) Unified Memory Extension

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

304

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