TDA4VM21 datasheet(315/331 Pages) TI

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Once component values have been selected to satisfy the maximum trigger voltage as described above, the

system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an

output voltage of 0.45 V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input

leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result

is a minimum trigger threshold of 4.008 V.

This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.

Approximately 250 mV of this range is introduced by VMON_ER_VSYS input threshold accuracy of ±3%,

approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this

range is introduced by loading error when VMON_ER_VSYS input leakage current is 2.5 μA.

The resistor values selected in this example produces approximately 100 μA of bias current through the resistor

divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to

about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor

divider bias current vs loading error is something the system designer needs to consider when selecting

component values.

The system designer should also consider implementing a noise filter on the voltage divider output since

VMON_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done

by installing a capacitor across R1 as shown in Figure 8-5. However, the system designer must determine the

response time of this filter based on system supply noise and expected response to transient events.

Figure 8-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger

threshold is -10% or 4.5 V.

Device

VMON_VSYS

SPRSP56_VMON_ER_MON_01

VSS

4.81 k

Ω

40.2 k

Ω ±

VSYS

Value = Determined by system designer

(System Power Supply)

Figure 8-5. System Supply Monitor Voltage Divider Circuit

8.3.6 High Speed Differential Signal Routing Guidance

The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed

differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and

spacing limits. TI supports only designs that follow the board design guidelines contained in the application

report.

8.3.7 Thermal Solution Guidance

The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful

implementation of a thermal solution for system designs containing this device. This document provides

background information on common terms and methods related to thermal solutions. TI only supports designs

that follow system design guidelines contained in the application report.

www.ti.com

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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