TDA4VM21 datasheet(313/331 Pages) TI

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MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

device clock input

J7ES_OSPI_Board_03

MCU_OSPI[x]_DQS

OSPI device DQS

OSPI/QSPI/SPI

device IOy, CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.

Figure 8-3. OSPI Interface High Level Schematic

8.3.3 SERDES REFCLK Design Guidelines

The following section details the routing guidelines that must be observed when terminating the SERDES

REFCLK and is applicable only when SERDES REFCLK is configured to input mode.

1. 50 Ω to GND is recommended on each leg.

2. Internal AC coupling is always enabled, so external biasing is not needed.

8.3.4 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5 V for normal operation, and as high as

20 V when the Power Delivery addendum is supported. Some applications require a max voltage to be 30 V.

The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in the

Figure 8-4), which limits the voltage applied to the actual device pin (USB0_VBUS, USB1_VBUS). The tolerance

of these external resistors should be equal to or less than 1%, and the leakage current of zener diode at 5 V

should be less than 100 nA.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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TDA4VM21 Datasheet(PDF) 313 Page - Texas Instruments