TDA4VM21 datasheet(309/331 Pages) TI

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Table 8-2. Isolated MCU and Main Voltage Domain Power Rail Mapping (continued)

TYPES

VOLTAGE [V]

DOMAIN NAMES

DOMAIN

GROUPS

POWER RAILS

Digital, low

voltage

0.80

VDD_CORE,

(VDDA_0P8_SERDES,

VDDA_0P8_SERDES_C,

VDDA_0P8_DP,

VDDA_0P8_DP_C,

VDDA_0P8_DSITX,

VDDA_0P8_DSITX_C,

VDDA_0P8_CSIRX,

VDDA_0P8_UFS,

VDDA_0P8_USB)8

VDD_CORE,

VDDA_0P8_<p

hy>8

VDD_CORE_0V8

Digital, low

voltage

0.85

VDDAR_CORE, VDDAR_CPU

VDDAR

VDD_RAM_0V85

Digital, low

voltage

1.1

VDDS_DDR_BIAS,VDDS_DDR,

VDDS_DDR_C

VDDS_DDR

VDD_DDR_1V1

1. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 3.3V to

support 3.3V digital interfaces

2. Any MCU or Main dual voltage IO supplies (VDDSHVn_MCU or VDDSHVn) being supplied by 1.8V to

support 1.8V digital interfaces

3. VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3/1.8V) power rail is required

for compliant, high-speed SD card operations. If SD card is not needed or standard data rates with fixed

3.3V operation is acceptable, then domain can be grouped with digital IO 3.3V power rail. If a SD card is

capable of operating with fixed 1.8V, then domain can be grouped with digital IO 1.8V power rail.

4. VDDA_3P3_USB is 3.3V analog domain used for USB 2.0 differential interface signaling. A low noise,

analog supply is recommended to provide best signal integrity for USB data eye mask compliance. If USB

interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3V digital IO

power rail either directly or through a supply filter.

5. VDDA_1P8_<phy> are 1.8V analog domains supporting multiple serial PHY interfaces. A low noise, analog

supply is recommended to provide best signal integrity, interface performance and spec compliance. If any of

these interfaces are not needed, data bit errors or non-compliant operation can be tolerated, then domains

can be grouped with digital IO 1.8V power rail either directly or through an in-line supply filter is allowed.

6. VDD_MMC0 is 1.8V digital supply supporting MMC0 signaling for eMMC interface. If MMC0 or eMMC0

interface is not needed, then domain can be grouped with digital IO 1.8V power rail. However, if MMC0

interface is needed, then VDD_MMC0 must not start ramp-up until VDD_CORE has reached VOPR MIN.

7. VDD_MCU is a digital voltage supply with a wide operational voltage range and power sequencing flexibility,

enabling it to be grouped and ramped-up with either 0.8V VDD_CORE or 0.85V RAM array domains

(VDDAR_xxx).

8. VDDA_1P8_<clk/pll/ana> are 1.8V analog domains supporting clock oscillator, PLL and analog circuitry

needing a low noise supply for optimal performance.

8.2 Device Connection and Layout Fundamentals

8.2.1 Power Supply Decoupling and Bulk Capacitors

8.2.1.1 Power Distribution Network Implementation Guidance

The Jacinto 7 Processor Power Distribution Networks: Implementation and Analysis (SPRACN5) provides

guidance for successful implementation of the power distribution network. This includes PCB stackup guidance

as well as guidance for optimizing the selection and placement of the decoupling capacitors. TI supports only

designs that follow the board design guidelines contained in the application report.

8.2.2 External Oscillator

For more information, see Section 6.9.4.1, Input and output Clocks/Oscillators.

www.ti.com

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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