TDA4VM21 datasheet(310/331 Pages) TI

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8.2.3 JTAG and EMU

Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various

debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target

Connection Guide.

For more recommendations on EMU routing, see Emulation and Trace Headers Technical Reference Manual

8.2.4 Reset

The device incorporates four external reset pins (MCU_PORz, MCU_RESETz, PORz, and RESET_REQz) and

four reset status pins (MCU_PORz_OUT, MCU_RESETSTATz, PORz_OUT, and RESETSTATz). These pins can

be driven by an external power good circuitry or Power Management IC (PMIC). MCU_PORz and Main PORz

pins should be held active low during the entire power-up phase, and until all power supplies as well as the

HFOSC0 clock are stable.

All MCU domain resets act as master resets to the whole device, whereas Main domain resets only reset Main

domain (MCU domain is reset isolated from all Main domain resets).

8.2.5 Unused Pins

For more information about Unused Pins, see Connections for Unused Pins

8.2.6 Hardware Design Guide for JacintoTM 7 Devices

The Hardware Design Guide for JacintoTM 7 Devices document describes hardware system design

considerations for the JacintoTM 7 family of processors.This design guide is intended to be used as an aid

during the development of application hardware.

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

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TDA4VM21 Datasheet(PDF) 310 Page - Texas Instruments