TDA4VM21 datasheet(311/331 Pages) TI

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8.3 Peripheral- and Interface-Specific Design Information

8.3.1 LPDDR4 Board Design and Layout Guidelines

The goal of the Jacinto 7 LPDDR4 Board Design and Layout Guidelines is to make the LPDDR4 system

implementation straightforward for all designers. Requirements have been distilled down to a set of layout and

routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.

TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.

8.3.2 OSPI and QSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI and QSPI

interfaces.

8.3.2.1 No Loopback and Internal Pad Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm

as stripline or ~8cm as microstrip)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-1

• Propagation delays and matching:

– A to B < 450 ps

– Matching skew: < 60 ps

MCU_OSPI[x]_CLK

OSPI/QSPI/SPI

device clock input

OSPI/QSPI/SPI

device IOy, CS#

MCU_OSPI[x]_D[y],

MCU_OSPI[x]_CSn[z]

OSPI_Board_01

* 0 Ω resistor (R1), located as close as possible to the MCU_OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

Figure 8-1. OSPI Interface High Level Schematic

8.3.2.2 External Board Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The MCU_OSPI[x]_LBCLKO output signal must be looped back into the MCU_OSPI[x]_DQS input

• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B)

should be approximately equal to half of the signal propagation delay from the MCU_OPSI[x]_LBCLKO pin to

the MCU_OSPI[x]_DQS pin ((C to D)/2). See the note below.

• The signal propagation delay from the MCU_OSPI[x]_CLK pin to the flash device CLK input pin (A to B) must

be approximately equal to the signal propagation delay of the control and data signals between the flash

device and the SoC device (E to F, or F to E)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 8-2

• Propagation delays and matching:

– A to B = E to F = (C to D) / 2

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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