TDA4VM21 datasheet(255/331 Pages) TI

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6.9.5.17 MCASP

For more details about features and additional description information on the device Multichannel Audio Serial

Port, see the corresponding sections within Section 5.3, Signal Descriptions and Section 7, Detailed Description.

Table 6-68 and Figure 6-84 present timing requirements for MCASP0 to MCASP11.

Table 6-67 represents MCASP timing conditions.

Table 6-67. MCASP Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.7

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

100

1100

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

Table 6-68. MCASP Timing Requirements

NO.

MODE(1)

MIN

MAX UNIT

ASP1 tc(AHCLKRX)

Cycle time, MCASP[x]_AHCLKR/X

15.26

ASP2 tw(AHCLKRX)

Pulse duration, MCASP[x]_AHCLKR/X high or low

0.5P(2) -

1.53

ASP3 tc(ACLKRX)

Cycle time, MCASP[x]_ACLKR/X

15.26

ASP4 tw(ACLKRX)

Pulse duration, MCASP[x]_ACLKR/X high or low

0.5R(3) -

1.53

ASP5 tsu(AFSRX-ACLKRX)

Setup time, MCASP[x]_AFSR/X input valid before

MCASP[x]_ACLKR/X

ACLKR/X int

12.3

ACLKR/X ext in/out

ASP6 th(ACLKRX-AFSRX)

Hold time, MCASP[x]_AFSR/X input valid after

MCASP[x]_ACLKR/X

ACLKR/X int

-1

ACLKR/X ext in/out

1.6

ASP7 tsu(AXR-ACLKRX)

Setup time, MCASP[x]_AXR input valid before

MCASP[x]_ACLKR/X

ACLKR/X int

12.3

ACLKR/X ext in/out

ASP8 th(ACLKRX-AXR)

Hold time, MCASP[x]_AXR input valid after

MCASP[x]_ACLKR/X

ACLKR/X int

-1

ACLKR/X ext in/out

1.6

(1)

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2)

P = AHCLKR/X period in ns.

(3)

R = ACLKR/X period in ns.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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