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TDA4VM21 Datasheet(PDF) 253 Page - Texas Instruments |
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TDA4VM21 Datasheet(HTML) 253 Page - Texas Instruments |
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253 / 331 page  - Open drain with weak pull-up - Open drain with weak pull-up SCL SDA O 2 D O 1 D Start Stop Repeated Start Stop 0.7xVDD 0.3xVDD 0.7xVDD 0.3xVDD O 3 D O 5 D OD4 OD6 Figure 6-81. I3C Open Drain Timing Requirements Table 6-63. I3C Push-Pull Timing Requirements - SDR and HDR-DDR Modes Figure 6-82 and Figure 6-83 NO. MODE MIN MAX UNIT D8 th(sclV-sdaV) Hold time, SDA valid after SCL transition Master tr(scl) + 3 and tf(scl) + 3 ns D9 tsu(sdaV-sclV) Seutp time, SDA valid before SCL transition Master 3 ns Table 6-64. I3C Push-Pull Switching Characteristics - SDR and HDR-DDR Modes see Figure 6-83, Figure 6-82 NO. PARAMETER MODE MIN MAX UNIT D1 tc(scl) Cycle time, SCL Master 80 100000 ns D2 tw(sclL) Pulse duration, SCL low Master 24 ns tw(sclL_dig) 32 ns D4 tw(sclH) Pulse duration, SCL high Master 24 ns tw(sclH_dig) 32 ns D6 tr(scl) Rise time, SCL Master 150 × 1 / tc(scl) 60 ns D7 tf(scl) Fall time, SCL Master 150 × 1 / tc(scl) 60 ns D10 td(Sr-sclV) Delay time, SCL valid after Repeated START (Sr) Master td(sclV-START), min ns D11 td(sclV-Sr) Delay time, Repeated START (Sr) after SCL valid Master td(sclV-START), min / 2 ns SCL SDA D1 D2 D8 D9 Start Stop Repeated Start Stop 0.7xVDD 0.3xVDD 0.7xVDD 0.3xVDD D4 D11 D10 D8 D9 D8 D9 D8 D9 Figure 6-82. I3C Push-Pull Timing Requirements - HDR-DDR Mode SCL SDA D1 D2 D8 D9 Start Stop Repeated Start Stop 0.7xVDD 0.3xVDD 0.7xVDD 0.3xVDD D4 D11 D10 Figure 6-83. I3C Push-Pull Timing Requirements - SDR Mode www.ti.com TDA4VM-Q1, TDA4VM SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 253 Product Folder Links: TDA4VM-Q1 TDA4VM |
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