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TDA4VM21 Datasheet(PDF) 250 Page - Texas Instruments

Part # TDA4VM21
Description  TDA4VM Processors
PDF  331 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TDA4VM21 Datasheet(HTML) 250 Page - Texas Instruments

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NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
LFD10
td(ckL/cknH-csnH)
Delay time, last falling HYPERBUS0_CK (rising HYPERBUS0_Ckn)
edge to HYPERBUS0_CSn[1:0] rising
0.33
ns
LFD11
td(ckV/cknV-rwdsV)
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_RWDS valid
1.13
3.68
ns
LFD12
td(ckV/cknV-dV)
Delay time, HYPERBUS0_CK/CKn transition to
HYPERBUS0_DQ[7:0] valid
1.16
3.84
ns
HYPERBUS_TIMING_01
CK, CKn
D8/LFD8
D2
RWDS
DQ[7:0]
D9/LFD9
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
CK and Data are center aligned
Host drives DQ[7:0] and RWDS
39:32
31:24
23:16
15:8
7:0
47:40
Dn
Dn
Dn+1 Dn+1
A
B
A
B
D6/LFD6
D7/LFD7
D11/LFD11
D10/LFD10
D12/LFD12
D4
D12/LFD12
CSn
Figure 6-78. HyperBus Timing Diagrams – Transmitter Mode
HYPERBUS_TIMING_02
RWDS
DQ[7:0]
Command-Address
Host drives DQ[7:0] and Memory drives RWDS
CK and Data are center aligned
Host drives DQ[7:0] and RWDS
39:32
31:24
23:16
15:8
7:0
47:40
Dn
Dn
Dn+1 Dn+1
A
B
A
B
CK, CKn
D8/LFD8
D2
D9/LFD9
D6/LFD6
D7/LFD7
D10/LFD10
D4
D12/LFD12
D5/LFD5
D5/LFD5
CSn
Figure 6-79. HyperBus Timing Diagrams – Receiver Mode
D3
D1
RESETn
HYPERBUS_TIMING_03
CSn
Figure 6-80. HyperBus Timing Diagrams – Reset
For more information, see HyperBus Interface section in Peripherals chapter in the device TRM.
TDA4VM-Q1, TDA4VM
SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024
www.ti.com
250
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: TDA4VM-Q1 TDA4VM



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