PM7384 datasheet(21/358 Pages) PMC

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PM7384 FREEDM-84P672

DATA SHEET

PMC-1990445

ISSUE 5

FRAME ENGINE AND DATA LINK MANAGER 84P672

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PIN DESCRIPTION

Table 1 – SBI Interface Signals (30)

Pin Name

Type

No.

Function

REFCLK

Input

AB3

The SBI reference clock signal (REFCLK)

provides reference timing for the SBI ADD and

DROP busses.

REFCLK is nominally a 50% duty cycle clock

of frequency 19.44 MHz ±50ppm.

FASTCLK

Input

The high-speed reference clock signal

(FASTCLK) is used by the FREEDM-84P672

to generate an internal clock for use when

processing DS-3 links.

FASTCLK is nominally a 50% duty cycle,

±50ppm clock having one of the following

frequencies: 51.84 MHz, 44.928 MHz or

66 MHz.

C1FP

Input

AE5

The C1 octet frame pulse signal (C1FP)

provides frame synchronisation for devices

connected via an SBI interface. C1FP must

be asserted for 1 REFCLK cycle every 500 µs

or multiples thereof (i.e. every 9720 n

REFCLK cycles, where n is a positive integer).

All devices interconnected via an SBI

interface must be synchronised to a C1FP

signal from a single source.

C1FP is sampled on the rising edge of

REFCLK.

Note – If the SBI bus is being operated in

synchronous mode [Ref. 4], C1FP must be

asserted for 1 REFCLK cycle every 6 ms or

multiples thereof.

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