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PM7384 Datasheet(PDF) 79 Page - PMC-Sierra, Inc |
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PM7384 Datasheet(HTML) 79 Page - PMC-Sierra, Inc |
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79 / 358 page  PM7384 FREEDM-84P672 DATA SHEET PMC-1990445 ISSUE 5 FRAME ENGINE AND DATA LINK MANAGER 84P672 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 68 Transmit Channel Descriptor Reference Table The TMAC672 maintains a Transmit Channel Descriptor Reference (TCDR) table in which is stored certain information relating to DMA activity on each channel together with TD pointers which are used by the TMAC672 to sort packet chains supplied by the host into per-channel linked lists (see below). The caching of DMA-related information reduces the number of host bus accesses required to process each data packet, while the sorting into per-channel linked lists eliminates head of line blocking. Each channel is provided with two entries in the TCDR table, one for high priority packets (Pri 1) and one for low priority packets (Pri 0). The structure of the TCDR table is shown in Figure 13 below. Figure 13 – Transmit Channel Descriptor Reference Table Current TD Pointer [14:0] Last TD Pointer [14:0] Host TD Pointer [14:0] DMA Current Address[31:0] Bit 0 Bit 33 TCC 0, Pri 0 TCC 671, Pri 1 Bytes to Tx [15:0] Reserved (12) Res Next TD Pointer [14:0] D A MCE IOC Abrt PiP NA U Res V TCC 1, Pri 0 Current TD Pointer [14:0] Last TD Pointer [14:0] Host TD Pointer [14:0] DMA Current Address[31:0] Bytes to Tx [15:0] Reserved (12) Res Next TD Pointer [14:0] D A MCE IOC Abrt PiP NA V Current TD Pointer [14:0] Last TD Pointer [14:0] Host TD Pointer [14:0] DMA Current Address[31:0] Bytes to Tx [15:0] Reserved (12) Res Next TD Pointer [14:0] D A MCE IOC Abrt PiP NA V U Res U Res Res Res Res Res Res Res |
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