PM7384 datasheet(13/358 Pages) PMC

13 / 358 page

PM7384 FREEDM-84P672

DATA SHEET

PMC-1990445

ISSUE 5

FRAME ENGINE AND DATA LINK MANAGER 84P672

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

· For each channel, the HDLC transmitter supports programmable flag

sequence generation, bit stuffing and frame check sequence generation. The

transmitter supports the generation of both CRC-CCITT and CRC-32 frame

check sequences. The transmitter also aborts packets under the direction of

the host or automatically when the channel underflows.

· Supports two levels of non-preemptive packet priority on each transmit

channel. Low priority packets will not begin transmission until all high priority

packets are transmitted.

· Alternatively, for each channel, the transmitter supports a transparent mode

where each octet is inserted transparently from host memory. For

channelised links, the octets are aligned with the transmit time-slots.

· Provides 32 Kbytes of on-chip memory for partial packet buffering in both the

transmit and receive directions. This memory may be configured to support a

variety of different channel configurations from a single channel with 32

Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of

buffering.

· Supports PCI burst sizes of up to 256 bytes for transfers of packet data.

· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board

test purposes.

· Supports 3.3 Volt PCI signaling environment.

· Supports 3.3 Volt I/O on non-PCI signals.

· Low power 2.5 Volt 0.25 mm CMOS technology.

· 352 pin enhanced ball grid array (SBGA) package.

PM7384 Datasheet(PDF) 13 Page - PMC-Sierra, Inc