PM7384 datasheet(3/358 Pages) PMC

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PM7384 FREEDM-84P672

DATA SHEET

PMC-1990445

ISSUE 5

FRAME ENGINE AND DATA LINK MANAGER 84P672

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

CONTENTS

FEATURES...............................................................................................1

APPLICATIONS........................................................................................3

REFERENCES .........................................................................................4

APPLICATION EXAMPLES ......................................................................5

BLOCK DIAGRAM....................................................................................6

DESCRIPTION .........................................................................................7

PIN DIAGRAM ..........................................................................................9

PIN DESCRIPTION ................................................................................10

FUNCTIONAL DESCRIPTION ...............................................................33

9.1

SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE

.....................................................................................................33

9.2

HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL.........34

9.3

SBI EXTRACTER AND PISO.......................................................35

9.4

RECEIVE CHANNEL ASSIGNER ................................................35

9.4.1

LINE INTERFACE..........................................................37

9.4.2

PRIORITY ENCODER ...................................................38

9.4.3

CHANNEL ASSIGNER ..................................................38

9.4.4

LOOPBACK CONTROLLER .........................................38

9.5

RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER...38

9.5.1

HDLC PROCESSOR .....................................................39

9.5.2

PARTIAL PACKET BUFFER PROCESSOR ..................39

9.6

RECEIVE DMA CONTROLLER ...................................................41

9.6.1

DATA STRUCTURES ....................................................42

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