PM7384 datasheet(49/358 Pages) PMC

49 / 358 page

PM7384 FREEDM-84P672

DATA SHEET

PMC-1990445

ISSUE 5

FRAME ENGINE AND DATA LINK MANAGER 84P672

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.4.2 Priority Encoder

The priority encoder monitors the line interfaces for requests and synchronises

them to the SYSCLK timing domain. Requests are serviced on a fixed priority

scheme where highest to lowest priority is assigned from the line interface

attached to link 0 to that attached to link 83. Thus, simultaneous requests from

link ‘m’ will be serviced ahead of link ‘n’, if m < n. When there are no pending

requests, the priority encoder generates an idle cycle. In addition, once every

fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests

are serviced. This cycle is used by the channel assigner downstream for host

microprocessor accesses to the provisioning RAMs.

9.4.3 Channel Assigner

The channel assigner block determines the channel number of the data byte

currently being processed. The block contains a 2688 word channel provision

RAM. The address of the RAM is constructed from concatenating the link

number and the time-slot number of the current data byte. The fields of each

RAM word include the channel number and a time-slot enable flag. The time-slot

enable flag labels the current time-slot as belonging to the channel indicted by

the channel number field.

9.4.4 Loopback Controller

The loopback controller block implements the channel based diagnostic

loopback function. Every valid data byte belonging to a channel with diagnostic

loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer

block (THDL672) is written into a 256 word FIFO. The loopback controller

monitors for an idle time-slot or a time-slot carrying a channel with diagnostic

loopback enabled. If either conditions hold, the current data byte is replaced by

data retrieved from the loopback data FIFO.

9.5 Receive HDLC Processor / Partial Packet Buffer

The Receive HDLC Processor / Partial Packet Buffer block (RHDL672)

processes up to 672 synchronous transmission HDLC data streams. Each

channel can be individually configured to perform flag sequence detection, bit

de-stuffing and CRC-CCITT or CRC-32 verification. The packet data is written

into the partial packet buffer. At the end of a frame, packet status including CRC

error, octet alignment error and maximum length violation are also loaded into

the partial packet buffer. Alternatively, a channel can be provisioned as

transparent, in which case, the HDLC data stream is passed to the partial packet

buffer processor verbatim.

PM7384 Datasheet(PDF) 49 Page - PMC-Sierra, Inc

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