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PM7384 Datasheet(PDF) 61 Page - PMC-Sierra, Inc

Part # PM7384
Description  FRAME ENGINE AND DATA LINK MANAGER 84P672
PDF  358 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7384 Datasheet(HTML) 61 Page - PMC-Sierra, Inc

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PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
50
Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword,
i.e. 32 bits. When the RMAC672 block writes a STATUS+RPDR to the ready
queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is
unmodified.
Figure 7 – RPDRR Queue Operation
Rx Packet Descriptor Reference Ready Queue
Bit 0
Bit 31
RPDRRQ_START_ADDR
RPDRRQ_EN D_ADDR
RPDR RQ_READ_ADDR
RPDRRQ_W RITE_ADDR
RPD - 16 bytes
RPD - 16 bytes
RPD - 16 bytes
RPD - 16 bytes
RPD - 16 bytes
buffer
-packet M
buffer
-packet N
buffer
-start of
packet O
buffer
-m iddle of
packet O
buffer
-end of
packet O
STATUS + RPDR
STATUS + RPDR
STATUS + RPDR
Receive Channel Descriptor Reference Table
On a per-channel basis, the RMAC672 caches information such as the current
DMA information in a Receive Channel Descriptor Reference (RCDR) Table.
The RMAC672 can process 672 channels and stores three dwords of
information per channel. This information is cached internally in order to



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