PM7384 datasheet(71/358 Pages) PMC

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PM7384 FREEDM-84P672

DATA SHEET

PMC-1990445

ISSUE 5

FRAME ENGINE AND DATA LINK MANAGER 84P672

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

and the packet status information associated with the data in each buffer. TDs

are transferred from the TMAC672 to the host and vice versa using descriptor

reference queues. The TMAC672 maintains all the pointers for the operation of

the queues. The TMAC672 acquires buffers with data ready for transmission by

reading TDRs from a TDR ready queue. After a packet has been transmitted,

the TMAC672 places the associated TDR onto a TDR free queue.

To minimise host bus accesses, the TMAC672 maintains a descriptor reference

table to store current DMA information. This table contains separate DMA

information entries for up to 672 transmit channels. The TMAC672 also

performs per-channel sorting of packets received in the TDR ready queue to

eliminate head-of-line blocking.

9.8.1 Data Structures

The TMAC672 communicates with the host using Transmit Descriptors (TD),

Transmit Descriptor References (TDR), the Transmit Data Reference Ready

(TDRR) queue and the Transmit Data Reference Free (TDRF) queue.

The TMAC672 reads packet data from data buffers in host memory. The TD,

TDR, TDRR queue, and TDRF queue are data structures which are used to

transfer host memory data buffer information. All four data structures are

manipulated by both the TMAC672 and the host computer. The TD holds the

data buffer size, data buffer address, and other packet information. The TDR is

a pointer which is used to index into a table of TDs. The TDRR queue and TDRF

queue allow the TMAC672 and the host to pass TDRs back and forth. These

data structures are described in more detail in the following sections.

Transmit Descriptor

The Transmit Descriptors (TDs) pass buffer and packet information between the

TMAC672 and the host. Both the TMAC672 and the host read and write

information in the TDs. TDs are stored in host memory in a Transmit Descriptor

Table. The Transmit Descriptor structure is shown in Figure 10.

Figure 10 – Transmit Descriptor

Bit 31

Data Buffer Start Address [31:0]

Bytes In Buffer [15:0]

TM AC Next TD P ointer[14:0]

IOC

AB T

Host Next TD P ointer[14 :0]

Transm it Buffer Size[15:0]

Res (2)

Reserved (16)

TCC[9:0]

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