HTG2190 datasheet(11/50 Pages) HOLTEK

11 / 50 page

HTG2190

Rev. 1.20

July 5, 2002

higher-order byte of the table word are transferred to

the TBLH. The Table Higher-order byte register

(TBLH) is read only. The Table Pointer (TBHP, TBLP)

is a read/write register (1FH, 07H), used to indicate

the table location. Before accessing the table, the lo-

cation must be placed in TBLP. The TBLH is read only

and cannot be restored. If the main routine and the

ISR (Interrupt Service Routine) both employ the table

read instruction, the contents of the TBLH in the main

routine are likely to be changed by the table read in-

struction used in the ISR. If this happens errors can

occur. In other words, using the table read instruction

in the main routine and the ISR simultaneously should

be avoided. However, if the table read instruction has

to be applied in both the main routine and the ISR, the

interrupt(s) should be disabled prior to the table read

instruction. It should not be enabled until the TBLH

has been backed up. All table related instructions

need two cycles to complete the operation. These ar-

eas may function as normal program memory de-

pending upon requirements.

Stack register

- STACK

This is a special part of memory which is used to save

the contents of the program counter (PC) only. The

stack is organized into 8 levels and is neither part of the

data nor program space, and is neither readable nor

writeable. The activated level is indexed by the stack

pointer (SP) and is neither readable nor writeable. At a

subroutine call or interrupt acknowledgment, the con-

tents of the program counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, sig-

naled by a return instruction (RET or RETI), the program

counter is restored to its previous value from the stack.

After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place,

the interrupt request flag will be recorded but the acknowl-

edge will be inhibited. When the stack pointer is decre-

mented (by RET or RETI), the interrupt will be serviced.

This feature prevents stack overflow allowing the pro-

grammer to use the structure more easily.

In a similar case, if the stack is full and a CALL is subse-

quently executed, stack overflow occurs and the first en-

try will be lost (only the most recent eight return address

are stored).

Data memory

- RAM

· Bank 0 (BP4~BP0=00000)

The Bank 0 data memory includes special purpose

and general purpose memory. The special purpose

memory is addressed from 00H to 3FH. All data mem-

ory areas can handle arithmetic, logic, increment,

decrement and rotate operations directly. Except for

some dedicated bits, each bit in the data memory can

be set and reset by the SET [m].i and CLR [m].i in-

structions, respectively. They are also indirectly ac-

cessible through the memory pointer registers

(MP0;01H, MP1;03H).

· Bank 1~11 (BP4~BP0=0001B~1011B)

The range of RAM starting from 40H to FFH are for

general purpose. Only MP1 can deal with the memory

of this range.

T M R 2

T M R 2 C

I N T C 1

T B H P

T M R 3

T M R 3 C

P W M C

P W M

X ' T A L C

C O L 3

C o m m o n P a d A d d r e s s R o t a t o r

D / A D a t a L o w e r - o r d e r B y t e R e g i s t e r

D / A D a t a H i g h e r - o r d e r B y t e R e g i s t e r

V o l u m e C o n t r o l R e g i s t e r

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 . H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

I A R 0

M P 0

I A R 1

M P 1

B P

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C 0

T M R 0 H

T M R 0 L

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P E

P E C

P A I / O D a t a R e g i s t e r

P A I / O C o n t r o l R e g i s t e r

P B I / O D a t a R e g i s t e r

P B I / O C o n t r o l R e g i s t e r

P C I / O D a t a R e g i s t e r

P C I / O C o n t r o l R e g i s t e r

P D I / O D a t a R e g i s t e r

P D I / O C o n t r o l

P E I / O D a t a R e g i s t e r

P E I / O C o n t r o l R e g i s t e r

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M e m o r y P o i n t e r 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M e m o r y P o i n t e r 1

B a n k P o i n t e r

A c c u m u l a t o r

P r o g r a m C o u n t e r L o w e r - b y t e R e g i s t e r

T a b l e P o i n t e r L o w e r - o r d e r B y t e R e g i s t e r

T a b l e H i g h e r - o r d e r B y t e R e g i s t e r

W a t c h d o g T i m e r O p t i o n S e t t i n g R e g i s t e r

S t a t u s R e g i s t e r

I n t e r r u p t C o n t r o l R e g i s t e r 0

T i m e r C o u n t e r 0 H i g h e r - o r d e r B y t e R e g i s t e r

T i m e r C o u n t e r 0 L o w e r - o r d e r B y t e R e g i s t e r

T i m e r C o u n t e r 0 C o n t r o l R e g i s t e r

T i m e r / E v e n t C o u n t e r 1 H i g h e r - o r d e r B y t e R e g i s t e r

T i m e r / E v e n t C o u n t e r 1 L o w - o r d e r B y t e R e g i s t e r

T i m e r / E v e n t C o u n t e r 1 C o n t r o l R e g i s t e r

S p e c i a l P u r p o s e

D a t a M e m o r y

I n t e r r u p t C o n t r o l R e g i s t e r 1

T a b l e P o i n t e r H i g h e r - o r d e r B y t e R e g i s t e r

T i m e r 2 R e g i s t e r

T i m e r 2 C o n t r o l R e g i s t e r

T i m e r 3 R e g i s t e r

T i m e r 3 C o n t r o l R e g i s t e r

X ' t a l . a s t O s c i l l a t o r u p C o n t r o l

P W M C o n t r o l

P W M D a t a

S e r i a l C o n t r o l

S e r i a l D a t a

C o l o r 0 P a l e t t e s

C o l o r 1 P a l e t t e s

C o l o r 2 P a l e t t e s

C o l o r 3 P a l e t t e s

B a n k 1 4 D a t a M e m o r y

( 1 2 8 B y t e )

G e n e r a l P u r p o s e

B a n k 0 D a t a M e m o r y

( 1 9 2 B y t e )

B a n k 1 5 D a t a M e m o r y

( 1 2 8 B y t e )

G e n e r a l P u r p o s e

B a n k 1 1 D a t a M e m o r y

( 1 9 2 B y t e )

G e n e r a l P u r p o s e

B a n k 1 D a t a M e m o r y

( 1 9 2 B y t e )

C O M R

D A L

D A H

V O L C

S E R C

S E R D A T A

C O L 0

C O L 1

C O L 2

1 D H

1 E H

1 . H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

2 9 H

2 A H

2 B H

2 C H

2 D H

2 E H

2 . H

3 0 H

3 1 H

3 2 H

3 3 H

3 . H

4 0 H

. . H

4 0 H

. . H

4 0 H

. . H

8 0 H

. . H

8 0 H

. . H

: U n u s e d

RAM mapping

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